Hi all,
Dual JFETs are often difficult to get and I didn't fancy selecting matched devices myself. Therefore, I've been looking at some hex PMOSFET/NMOSFET combinations that are also known as hex unbuffered inverters. Noise and offset are totally uncharacterised, of course, but they actually aren't too bad. I measured four SN74HCU04N's and ten SN74AHCU04N's and got by far the best results from the SN74AHCU04N's.
See the attached schematic. The numbers in the schematic are in Dutch, so the decimal separator is a comma rather than a point. The numbers below refer to the quad IC1A-IC1E-IC1B-IC1F. The noise measurements are based on quasi-peak-to-peak values measured with an oscilloscope, so they are not very accurate, but should be in the right ballpark. I used the 10 kohm+180 kohm as a known noise source to compare the IC1A-IC1E-IC1B-IC1F noise with.
SN74HCU04N, using R1=6.19 kohm and R2=15 kohm:
Average offset voltage: -6.32 mV
Sample standard deviation: 5.07 mV
Input leakage current: about 1 pA to 5.2 pA, but the measurement amplifier was actually clipping on mains hum
Equivalent input noise, measured on only one sample: about 30 nV/sqrt(Hz), A-weighted average (that is, white noise level that would give the same A-weighted noise as the actual noise of the four inverters, which is largely 1/f)
SN74AHCU04N, using R1=6.19 kohm and R2=15 kohm:
Average offset voltage: -0.289 mV
Sample standard deviation: 0.595 mV
Worst of ten: 1.697 mV
Input leakage current: between 22 pA and 50 pA
Noise, measured on two samples (first and ninth): respectively 19.6 nV/sqrt(Hz) and 19.2 nV/sqrt(Hz) A-weighted average
Ninth SN74AHCU04N remeasured using R1=6.19 kohm and R2=62.5 kohm:
about 11.3 nV/sqrt(Hz) A-weighted average
transconductance (entire stage) 3.3 mS
offset 0.305 mV
input leakage current 18 pA
Ninth SN74AHCU04N remeasured using R1=16.39 kohm and R2=138 kohm:
about 10.4 nV/sqrt(Hz) A-weighted average
transconductance (entire stage) 1.97 mS
offset 0.389 mV
input leakage current 17.9 pA
Ninth SN74AHCU04N remeasured using R1=16.39 kohm and R2=649 kohm:
about 8.1 nV/sqrt(Hz) A-weighted average
transconductance (entire stage) 1.68 mS
offset 0.585 mV
input leakage current 22.3 pA
What is clear is that the 1/f noise of the NMOSFETs is much worse than the 1/f noise of the PMOSFETs. This was to be expected: at equal gate area, PMOSFETs are usually better than NMOSFETs, and the difference gets even bigger because the PMOSFETs in an inverter actually have larger gates than the NMOSFETs. Anyway, bottom line is that the NMOS tail current should be much smaller than the PMOS tail current for low noise.
Regarding the schematic: depending on the type of measurement I wanted to do, I soldered the input wire to one of the four things shown left on the schematic. Thanks to the 50 kohm-100 ohm voltage divider, I could measure 501 times the actual offset using a simple digital multimeter. Using the 100 Mohm and comparing the measured offset with and without 100 Mohm, I could calculate the leakage current. The 10 nF MKT capacitor and a shielded box made sure the op-amp was not driven into clipping by picked-up mains hum.
For the noise measurements, I shorted the input to ground or connected it to 10 kohm+180 kohm, so I could compare the noise of the SN74AHCU04 to the known thermal noise of 190 kohm. The op-amp output was connected to an oscilloscope through a times 10 amplifier and A-weighting filter.
Best regards,
Marcel van de Gevel
Dual JFETs are often difficult to get and I didn't fancy selecting matched devices myself. Therefore, I've been looking at some hex PMOSFET/NMOSFET combinations that are also known as hex unbuffered inverters. Noise and offset are totally uncharacterised, of course, but they actually aren't too bad. I measured four SN74HCU04N's and ten SN74AHCU04N's and got by far the best results from the SN74AHCU04N's.
See the attached schematic. The numbers in the schematic are in Dutch, so the decimal separator is a comma rather than a point. The numbers below refer to the quad IC1A-IC1E-IC1B-IC1F. The noise measurements are based on quasi-peak-to-peak values measured with an oscilloscope, so they are not very accurate, but should be in the right ballpark. I used the 10 kohm+180 kohm as a known noise source to compare the IC1A-IC1E-IC1B-IC1F noise with.
SN74HCU04N, using R1=6.19 kohm and R2=15 kohm:
Average offset voltage: -6.32 mV
Sample standard deviation: 5.07 mV
Input leakage current: about 1 pA to 5.2 pA, but the measurement amplifier was actually clipping on mains hum
Equivalent input noise, measured on only one sample: about 30 nV/sqrt(Hz), A-weighted average (that is, white noise level that would give the same A-weighted noise as the actual noise of the four inverters, which is largely 1/f)
SN74AHCU04N, using R1=6.19 kohm and R2=15 kohm:
Average offset voltage: -0.289 mV
Sample standard deviation: 0.595 mV
Worst of ten: 1.697 mV
Input leakage current: between 22 pA and 50 pA
Noise, measured on two samples (first and ninth): respectively 19.6 nV/sqrt(Hz) and 19.2 nV/sqrt(Hz) A-weighted average
Ninth SN74AHCU04N remeasured using R1=6.19 kohm and R2=62.5 kohm:
about 11.3 nV/sqrt(Hz) A-weighted average
transconductance (entire stage) 3.3 mS
offset 0.305 mV
input leakage current 18 pA
Ninth SN74AHCU04N remeasured using R1=16.39 kohm and R2=138 kohm:
about 10.4 nV/sqrt(Hz) A-weighted average
transconductance (entire stage) 1.97 mS
offset 0.389 mV
input leakage current 17.9 pA
Ninth SN74AHCU04N remeasured using R1=16.39 kohm and R2=649 kohm:
about 8.1 nV/sqrt(Hz) A-weighted average
transconductance (entire stage) 1.68 mS
offset 0.585 mV
input leakage current 22.3 pA
What is clear is that the 1/f noise of the NMOSFETs is much worse than the 1/f noise of the PMOSFETs. This was to be expected: at equal gate area, PMOSFETs are usually better than NMOSFETs, and the difference gets even bigger because the PMOSFETs in an inverter actually have larger gates than the NMOSFETs. Anyway, bottom line is that the NMOS tail current should be much smaller than the PMOS tail current for low noise.
Regarding the schematic: depending on the type of measurement I wanted to do, I soldered the input wire to one of the four things shown left on the schematic. Thanks to the 50 kohm-100 ohm voltage divider, I could measure 501 times the actual offset using a simple digital multimeter. Using the 100 Mohm and comparing the measured offset with and without 100 Mohm, I could calculate the leakage current. The 10 nF MKT capacitor and a shielded box made sure the op-amp was not driven into clipping by picked-up mains hum.
For the noise measurements, I shorted the input to ground or connected it to 10 kohm+180 kohm, so I could compare the noise of the SN74AHCU04 to the known thermal noise of 190 kohm. The op-amp output was connected to an oscilloscope through a times 10 amplifier and A-weighting filter.
Best regards,
Marcel van de Gevel
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Very clever and interesting. 
A pity those transistors are tangled up with so many spurious things, like supply rails, protection and substrate diodes, and opposite sex inactive transistors (just like me
). This somewhat constraints the ways they can be used.
The 74HC4007 lifts some of those restrictions, unfortunately it is less readily available than the HCU04 or the CD4007 (this one is awfully noisy)
A pity those transistors are tangled up with so many spurious things, like supply rails, protection and substrate diodes, and opposite sex inactive transistors (just like me
). This somewhat constraints the ways they can be used.The 74HC4007 lifts some of those restrictions, unfortunately it is less readily available than the HCU04 or the CD4007 (this one is awfully noisy)
Very clever and interesting.
A pity those transistors are tangled up with so many spurious things, like supply rails, protection and substrate diodes, and opposite sex inactive transistors (just like me
True, but I don't consider that a big problem if you need a differential pair. Supply and ground rails are basically just the common source nodes of the differential pairs, where you connect the tail current sources to. (In my test circuit I used tail resistors for simplicity, but in the final circuit I will use current sources.) The protection diodes protect the transistors whether you use them as inverters or as differential pairs. You can get the diodes to always be in reverse as long as you don't overdrive anything. I use the NMOS side to bias the PNP cascodes that I've added to improve voltage handling. As long as the bias current for the NMOS side is much smaller than for the PMOS side, they don't degrade the noise performance.
One disadvantage of this approach is that the NMOS differential pair will increase distortion somewhat. When the NMOS side runs at a much lower current than the PMOS side for noise reasons, the NMOS pair has a much lower VGSeff and, hence, much lower signal handling than the PMOS side. A way around this could be to leave the VSS pin floating and derive the bias voltage for the cascodes in some other way, like with two diodes.
No, I haven't. I only looked at SN74HCU04 and SN74AHCU04, the SN74AHCU04 being the best by far.
I actually want to have two differential pairs connected to the same input nodes. One pair is going to be used as an input stage of a feedback amplifier and one as a clipping detector that monitors the error voltage. With a hex inverter I can crossquad four inverters for the input stage and use the other two for the clipping detector.
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