I am opening this new thread hoping to get some better insight regarding jfet implementations.
From reading Horowitz & Hill, I understand that for a given Vds, if we set
Vgs = 0, Ids is fixed at Idss.
If Vgs is reduced, Ids is also reduced until it stops (pinchof)
In this book, I found a picture with jfet characteristic curves where I can see Id = Idss for Vgs=0 but if Vgs >0 than Id is higher than Idss.
I also read elsewhere that one should never allow a positive Vgs because that could let the current flow from Drain to Gate with disastrous results.
So my first question is:
Can a jfet operate at Id higher than Idss ?
From reading Horowitz & Hill, I understand that for a given Vds, if we set
Vgs = 0, Ids is fixed at Idss.
If Vgs is reduced, Ids is also reduced until it stops (pinchof)
In this book, I found a picture with jfet characteristic curves where I can see Id = Idss for Vgs=0 but if Vgs >0 than Id is higher than Idss.
I also read elsewhere that one should never allow a positive Vgs because that could let the current flow from Drain to Gate with disastrous results.
So my first question is:
Can a jfet operate at Id higher than Idss ?
No. Read Borberly articles as Juma suggested. Also there is AN102 and AN103. Google it.
Operating a JFET at Id > Idss is not a problem per se, as long as you keep the Pd under dangerous level. The problem is that at Id > Idss significant current starts to flow through the gate. That way you lose the important property of JFET - the high input impedance and you are out of linear working regime.
That's not a big problem in switching mode but that's not what we here usually use the JFETS for.
That's not a big problem in switching mode but that's not what we here usually use the JFETS for.
Marshal Leach's class notes are a good resource.
http://users.ece.gatech.edu/mleach/ece3050/notes/jfet/thejfet.pdf
http://users.ece.gatech.edu/mleach/ece3050/notes/jfet/thejfet.pdf
Odd, If you let Vgs = 0 then apply a signal, the Vgs will swing between negative and positive. This is done all the time. In fact this is how MOST JFets are used in real circuits. So, how much is the input impedance changing? Does this matter? Does it create non-linearities? How large is the gate current?
Sometimes when used as current sources they are biased to a particular positive Vgs to produce a desired current flow... they don't fry then...
_-_-bear
Sometimes when used as current sources they are biased to a particular positive Vgs to produce a desired current flow... they don't fry then...
_-_-bear
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Hi,
Well, as Vgs becomes positive (for an NJFET) we find we have a diode between G & S that is now becoming forward biased.
As this is a silicone diode it will probably take a few 100mV before you get appreciable conduction.
So as long as no other limits are exceeded giving a J-Fet a litte extra positive gate voltage is not going to be the end of the world...
Ciao T
Well, as Vgs becomes positive (for an NJFET) we find we have a diode between G & S that is now becoming forward biased.
As this is a silicone diode it will probably take a few 100mV before you get appreciable conduction.
So as long as no other limits are exceeded giving a J-Fet a litte extra positive gate voltage is not going to be the end of the world...
Ciao T
Nchannel jFETs
Vgs cannot be reduced any further. Zero is Zero.
If Vgs is made -ve then the Id reduces.
If Vgs is made +ve then the Id increases.
J.Curl has posted that jFETs can work and do work with (small) +ve Vgs.
I cannot recall what he posted, if at all, on whether one could gain any advantage by setting the gate bias to slightly +ve.
Both conditions that Juma forewarns about, i.e. gate leakage and excess dissipation are mentioned by J.Curl.
BTW,
Pass B1 is exactly this high bias condition and small +ve Vgs.
Everyone that listens to a B1 is experiencing small +ve Vgs and yet all appear to confirm that the B1 works well.
If Vgs = zero volts i.e. G & S shorted, then Idss flows.
Vgs cannot be reduced any further. Zero is Zero.
If Vgs is made -ve then the Id reduces.
If Vgs is made +ve then the Id increases.
J.Curl has posted that jFETs can work and do work with (small) +ve Vgs.
I cannot recall what he posted, if at all, on whether one could gain any advantage by setting the gate bias to slightly +ve.
Both conditions that Juma forewarns about, i.e. gate leakage and excess dissipation are mentioned by J.Curl.
BTW,
Pass B1 is exactly this high bias condition and small +ve Vgs.
Everyone that listens to a B1 is experiencing small +ve Vgs and yet all appear to confirm that the B1 works well.
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generally a jFET CCS is obtained by inserting a resistor in the source circuit.
This results in a -ve Vgs.
The CCS current set by this method is less than Idss.
If the resistor value is reduced to Zero ohms, then the CCS current is the Idss.
One cannot with normal CCS assemblies get the CCS to be greater than Idss.
Satoru posted two graphs showing how much forward bias would be ok. I think this is what Andrew was referring to (posts 109 & 118):
http://www.diyaudio.com/forums/solid-state/120243-variation-jc-2-preamplifier-11.html
http://www.diyaudio.com/forums/solid-state/120243-variation-jc-2-preamplifier-12.html#post1477949
http://www.diyaudio.com/forums/solid-state/120243-variation-jc-2-preamplifier-11.html
http://www.diyaudio.com/forums/solid-state/120243-variation-jc-2-preamplifier-12.html#post1477949
Hi Thorsten
So if we set a jfet to work at Idss (Vgs=0 and Rs =0) we can input some signal and it ill swing current happily as long as we do not exceed max Id admisible by the jfet.
If input signal does not exceed 100mV there should be no damage. That is ok if you use a 0.5mV cart as the input
How can we determine max Id for a given jfet...? I did not find that info in the 2sk170 for instance.
Hi Martin
It seems you already found the answer to my initial questions.
It is possible to set a jfet to work at Idss (and sometimes it will be good practice) so that input signal makes it swing Vgs pos Vgs neg, without much trouble.
Now second question is:
Is it good for THD ?
Is it good for noise ?
We get higher gain but what is the reverse of the coin ?
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