Hi all,
Any chance a few people could tear this to shreds for me, it is a mostly datasheetish ADC input stage and parts up to the adc chip itself. Clocking is at 27Mhz from a local clock module (not shown) giving an output sample rate of ~210Khz, which is then downsampled by an SRC4192.
The reason for the That semi parts is that they are actually a much better line receiver then the Texas circuit, and this thing is expected to be driven from long cables with possibly large amounts of RF common mode on them, the input stage needs all the help it can get.
The reasoning behind the 8V rail for the ADC drivers is that these only have to swing a few volts and by lowering the supply rail to these parts I will reduce the heat generated.
Given I am putting up to 12 sets of these in a 2U rack with the corresponding DACs and possibly AES3 receivers (Plus a core 2 processor), and am trying to do it with pure convection cooling, I need all the help I can get in reducing heat dissipation.
The exact value of the gain setting resistors will depend on which standard I need (SMPTE Vs EBU).
Vprot is supplied via a resistor from the +- 15V rail, with capacitor and transorb to soak up any transients at the inputs.
The signal path is DC coupled, and HPF will be applied in the software as I don't like the filter in the ADC (it goes over too high and will cause phase errors at low frequency).
The 2N2 caps at the input form a passive low pass with the 100R resistors for differential mode signals to remove anything that might cause problems with the modulator and for common mode signals form a filter with the input common mode choke and the 100pf cap while still allowing the common mode bootstrap via the 4K7 resistor to work at low frequencies where the input stage still has gain.
Let the shredding begin!
Regards, Dan.
Any chance a few people could tear this to shreds for me, it is a mostly datasheetish ADC input stage and parts up to the adc chip itself. Clocking is at 27Mhz from a local clock module (not shown) giving an output sample rate of ~210Khz, which is then downsampled by an SRC4192.
The reason for the That semi parts is that they are actually a much better line receiver then the Texas circuit, and this thing is expected to be driven from long cables with possibly large amounts of RF common mode on them, the input stage needs all the help it can get.
The reasoning behind the 8V rail for the ADC drivers is that these only have to swing a few volts and by lowering the supply rail to these parts I will reduce the heat generated.
Given I am putting up to 12 sets of these in a 2U rack with the corresponding DACs and possibly AES3 receivers (Plus a core 2 processor), and am trying to do it with pure convection cooling, I need all the help I can get in reducing heat dissipation.
The exact value of the gain setting resistors will depend on which standard I need (SMPTE Vs EBU).
Vprot is supplied via a resistor from the +- 15V rail, with capacitor and transorb to soak up any transients at the inputs.
The signal path is DC coupled, and HPF will be applied in the software as I don't like the filter in the ADC (it goes over too high and will cause phase errors at low frequency).
The 2N2 caps at the input form a passive low pass with the 100R resistors for differential mode signals to remove anything that might cause problems with the modulator and for common mode signals form a filter with the input common mode choke and the 100pf cap while still allowing the common mode bootstrap via the 4K7 resistor to work at low frequencies where the input stage still has gain.
Let the shredding begin!
Regards, Dan.