Quote:
Originally Posted by eplpwr
Some technical questions on the RD-30:
- Are you generating the clock in the FPGA (soft PLL), or are you using crystal(s)?
- Is the Bytemorph DF oversampling to 768kHz or 384 kHz?
- Are you doing oversampling in integer multiples, or ASRC? I see only 384/768 kHz mentioned - for n x 44.1 kHz input I'd like to see 352.8 or 705.6 kHz.
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There are 2 main clocks involved, and both are external XO's. One is a high-frequency clock involved in sampling the input signal; second - and key of the reclocking system, combined with fpga internal ram buffer - is the Si570 DCO. This allows the creation of a PLL entirely in the digital domain (all-digital-pll). The performance of the ADPLL is essentially given by the performance of the Si570, which offers a remarkably low phase noise for a DCO.
The Bytemorph DF is actually a collection of 3 independent filters; they are indeed integers (no ASRC). There is a 8x filter for 44.1k and 48k; a 4x filter for 88.2 or 96k input; and a 2x filter for 176 and 192k. The filters are switched on-the-fly when sample rate changes. I will come back with detailed DF performance in the next posts.
Last edited by Lupulroz; 23rd September 2012 at 06:08 PM.
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