what are the meaurement conditions? - its easy to get milliOhm Z with feedback over audio frequencies - with VFA too
the AD811 I/V can't be an exception to this - its open loop -input Z is speced at 14 Ohms typ and it has to rely on loop feedback to reduce this value
milliOhms is impractical to achieve at DAC switching glitch energy frequencies - parasitic lead and trace inductance insure that
I'm not saying VFA are the best choice for audio DAC I/V - but its not clear what the errors the Golden Ears are hearing are when looking at recent VFA, FET or linearized BJT front end parts performance in I/V
and the input current noise of AD811, CFA as a class mean you may not be reaching the S/N spec of some flagship audio DACs
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Hawksford's multiloop op amp I/V ? - seems like someone should try it someday - it does have "Guru" cred...
http://www.essex.ac.uk/csee/researc...Current steering transimpedance amplifier.pdf
... multiloop accomplishes the separation of input perfomance from output load driving thermal effects - choose different, better speced op amps for each task
http://www.essex.ac.uk/csee/researc...Current steering transimpedance amplifier.pdf
... multiloop accomplishes the separation of input perfomance from output load driving thermal effects - choose different, better speced op amps for each task
Well qusp, I'm glad that you know everything that there is to know. I am just coming up to speed with digital reproduction. I have a very good idea about the OPPO, and I told the company that about 6 mo ago. I'm afraid that I didn't have much proof, just my ears.
And what IC would you chose?
And what IC would you chose?
To my consternation I recently learned that the well-regarded ESS DAC chip has a Zout of 781 ohms nominally on each phase. Not 'current output' in my book!
I remarked elsewhere that this is a schitzophrenic chip, not able to decide whether it should be a current out or a voltage out DAC. But maybe I was too harsh.
jan
And afaik, again no discussion/disclosure of the code dependence of that stiffish conductance. This leads to additional consternation for those who calculate, or observe, the noise gain when the ESS chips feed the I/V converter. A seemingly tractable few nV/sq rt Hz gets to be most annoying!
As well the ESS stuff is doubly consternating by its additionally schizoid and multiple personality disorder nature, as according to its makers, it is somehow more digital than analog. Rubbish of course, the continuation of the conflation of the symbol domain with the signal domain. See the writings of Bruno P. in this regard.
For the ESS, if I was constrained to ICs, or at least a similar budget and space to what they used, I would use the SMD monolithic Dual ALD mosfet network parts, with 4 internal fets, use 2 of them for CCS for the other 2, or SMD monolithic dual bipolar and perhaps a current mirror in front of something like the lme49724 as part of a composite opamp (much cheaper than its OPA1632/THS brethren). use the large order to negotiate tighter matching criterion on the fets.
High transconductance is mandatory to get the most out of this part due to the issues being discussed here at the moment ie. its low output impedance. that being said, you can get pretty excellent results from it in 'voltage output' mode as well, just not -120dB THD+N.
Its internal speed and higher demands of clock speed mean that the layout wrt RFI and its impact on noise cannot be ignored. Band limit the input of a fairly wide bandwidth circuit, but not overly wide bandwidth. Mosfet inputs possibly being preferred for their better innate rejection of RFI, vs the innate lower noise and high gm of BJTs
Feed the AVCC regulator into a /2 divider and leverage that to get rid of DC. keep the return path to the DAC AVCC supply pins from the IV stage as unobstructed and low impedance as possible. keep decoupling as close and small as possible for lowest inductance. Pay close attention to the decoupling of the DVDD supplies, in order to better isolate them and their internal logic from the more critical analogue pins. use steep passive filtering on all regs for the analogue pins and clock, for lowest noise. Others may disagree here, but I feel lowest noise is more important than low impedance or ultra-wide bandwidth for reference and clock supplies, as long as local decoupling is up to snuff; certainly if you are budget and space constrained.
With higher ambition and budget all manner of other options exist, but if going for best measured specs and 'current mode' output, it pretty much rules out jfets for the input differential due to impedance. Another barrier is its relatively high current of nearly 32mA in mono mode.
i'm not even close to knowing all there is to know, yet another example of your exaggerating the situation in order to try and make your case stronger. You havent been speaking from a humble lack of experience about this before, more like mentioning your vast experience before talking DACs and ICs down with generic hand-waving statements like before. You use 'authoritative voice' with a wide brush, but somehow disregard decades of research and implementation by others far more knowledgeable than me; a babe in the woods. this research and implementation has been repeatedly pointed out to you and you must have been surrounded by it in your position and NOW you say you are only just getting into digital?
jan: yes its not a typical current output DAC, but 780Ω isnt that unmanageable and its not like the Ti 179X chips are ideal current sources, its when people parallel them for dual mono and fail to take into account that this lowers each mono output less than 100Ω. All this effort and expense undertaken while not getting any better performance than what you can get with a single one. These people seem not to notice that the chip is built from the ground up, with convenient pinout and internal fully isolated L/R channels, so as long as your layout and power supply is dual mono, you have a dual mono dac. of course without 2 or more chips its not fashionably dual mono
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My guess is that they did the lowish Zout precisely to be able to parallel outputs just like that and reap some benefits from it.
Interestingly, while Oppo did that in earlier models (and switch the whole parallel bunch into whatever analog output was used at any moment), in the newer 105 they just use the separate outputs to feed all analog outs permanently.
I wonder why (but realise that cheaper implementation may have something to do with that).
Not saying the Oppo 105 isn't a great machine - it is for me.
But that, of course, comes from a myriad of other factors, which you can't all improve just with a different I/V opamp.
jan
perhaps because the diatribe here continues to be trotted out the same too?
all know you are a fanboi, you made that clear back then too ...
just sayin ...
its difficult enough to make the ENOB for a single ESS chip laid out as stereo balanced (4 parallel a channel, standard implementation with 195Ω Zout). given its fully dual mono already and using 2 you will still have the same difficulty making them count, plus more current to deal with ... i'm not sure the reasons are there on a purely engineering standpoint.
it has perhaps some marginal benefits for power supply layout and potential sales only IMO. there is more to be gained by spending some money on an FPGA for tweaking the internal digital filters/registers and clocking, but that does require some significant investment in staff.
just a different opamp? that by itself would be futile. I didnt suggest just a different opamp, almost nothing I mentioned above was done and I only scratched the surface, space and of course probably lack of interest in the audience here for my own recommendations are likely low enough.
when I was talking about monolithic duals and fets above, i'm not talking about opamps, i'm talking about dual or quad monolithic mosfets or dual monolithic bipolar transistors for the input stage, followed by a fully differential opamp as a composite opamp, but I touched on a few other areas that were seemingly ignored as well.
i'm sure it does its job quite well regardless and as you say there is more to this equation given its purpose, the ES9018 seems to be capable of pretty good performance even with suboptimal implementation, but it certainly presents some opportunities to get the best out of it.
Or drop a big cap right across the output and make a critically damped two pole TIA with a low noise VFA and suitable feedback cap. Now when the op-amp output impedance goes up a RF frequencies there is a cap right at the input to take over.
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I like your thinking, qusp - to me, every pin or link going into the DAC is a potential troublemaker, I would be absolutely paranoid about trying to optimise each connection here.
For me, the killer of digital sound has always been interference effects - even the roughest, standard, D/A section has put up a good show if I baby it really, really carefully ...
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