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Old 11th January 2010, 01:15 PM   #3461
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Well, I just returned from CES. I heard things that would not be believed here, saw cables as thick a 1 inch in diameter, connectors that sounded different, depending on what metal they were composed of, and some really pretty HDTV.
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Old 11th January 2010, 03:26 PM   #3462
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Moving forward. The amount of non-linear capacitance at the input of a solid state device changes with operating conditions. Change in input capacitance appears mostly to be connected with Vds in jfets. At least, the Toshiba audio jfets that we tend to use.
This CHANGE in input capacitance is a possible high frequency distortion generator. I have measured it, in the past. The amount of capacitance is important primarily in relation to the source impedance used. For example, a 100K input pot might be too much for a complementary differential Toshiba jfet input stage because the RinCin product would be too large. 10-20K might be preferred.
However, it is the CHANGE in input capacitance that really matters and this can be controlled by cascoding AND keeping a relatively high voltage (10-15V) across the input jfets (Vds). This minimizes the change in capacitance with signal.
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Old 12th January 2010, 12:56 PM   #3463
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John, are you saying that in the "worst case" with the JFETs being driven from a >~100kohm source that the effect of RinCin would be a LP filter that varies with signal level?

If not, what is the "source" of distortion that is being suggested?

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Old 12th January 2010, 01:11 PM   #3464
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Quote:
Originally Posted by john curl View Post
Moving forward. The amount of non-linear capacitance at the input of a solid state device changes with operating conditions. Change in input capacitance appears mostly to be connected with Vds in jfets. At least, the Toshiba audio jfets that we tend to use.
This CHANGE in input capacitance is a possible high frequency distortion generator. I have measured it, in the past. The amount of capacitance is important primarily in relation to the source impedance used. For example, a 100K input pot might be too much for a complementary differential Toshiba jfet input stage because the RinCin product would be too large. 10-20K might be preferred.
However, it is the CHANGE in input capacitance that really matters and this can be controlled by cascoding AND keeping a relatively high voltage (10-15V) across the input jfets (Vds). This minimizes the change in capacitance with signal.
If this would be true, a common source JFET stage would be kinda ideal PIM generator.

Fortunately, the input capacitance has little to nothing to do with Vds. Cgd does, but that's already beyond what you are grasping at this point about JFETs .
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Old 12th January 2010, 02:57 PM   #3465
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Quote:
Originally Posted by john curl View Post
Moving forward. The amount of non-linear capacitance at the input of a solid state device changes with operating conditions.
Change in input capacitance appears mostly to be connected with Vds in jfets.
At least, the Toshiba audio jfets that we tend to use.
This CHANGE in input capacitance is a possible high frequency distortion generator. I have measured it, in the past.
Would you mind sharing some Volts & picoFarads with us?

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Old 12th January 2010, 03:26 PM   #3466
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Gerhard, you just have to get a serious data sheet from the jfet manufacturer, and read it carefully. It shows the Ciss changing with Vds in a graph.
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Old 12th January 2010, 03:29 PM   #3467
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Actually, any semiconductor seems to be a PIM generator. I have been told this for years. Is it now that obvious? Good.
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Old 12th January 2010, 03:34 PM   #3468
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Originally Posted by john curl View Post
Gerhard, you just have to get a serious data sheet from the jfet manufacturer, and read it carefully. It shows the Ciss changing with Vds in a graph.
It would also help you to get some understanding of how Ciss is defined and what's the relationship between Ciss and the input capacitance, as seen by the signal source in a common source JFET stage.

Larry Page and Serghey Brin have lots of information about Ciss.
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Old 12th January 2010, 03:46 PM   #3469
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It would, and has been for decades, seem to me that Ciss, while a combination of Cgd and Cgs, is actually the best approximation of what any input generator sees. That is why I use it.
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Old 12th January 2010, 04:15 PM   #3470
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Originally Posted by john curl View Post
It would, and has been for decades, seem to me that Ciss, while a combination of Cgd and Cgs, is actually the best approximation of what any input generator sees. That is why I use it.
That is correct, up to a "small" detail. Ciss is Cgs in parallel with Cgd when the drain and source are shorted. Somehow, I'm pretty confident that's not how you use your JFETs.

Anyway, Cgd does not change because of the input signal, but because of the changes in Vds as a result of the input signal. That's why cascoding helps. A simple example of causal relationship.
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