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Old 6th January 2010, 12:19 PM   #3341
syn08 is offline syn08  Canada
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Well, that brings up my (somewhat naive) question- John says that paralleling two lower Idss devices doubles the input capacitance. I can see that it's double the input capacitance of one lower-Idss device, but in circuit, will the input capacitance be double that of a single device with twice the Idss?
Paralelling multiple devices for the same Idss won't lead to a significantly higher Ciss compared to a single device. Otherwise said, Ciss depends significantly on Idss (higher with higher Idss).

However, Crs depends weakly on Idss. By paralleling devices, Crs will increase. As Crs strongly depends on Vds, it is to be expected that paralleled devices will have a poorer frequency response and a poorer linearity.
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Old 6th January 2010, 01:52 PM   #3342
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Paralelling multiple devices for the same Idss won't lead to a significantly higher Ciss compared to a single device. Otherwise said, Ciss depends significantly on Idss (higher with higher Idss).

However, Crs depends weakly on Idss. By paralleling devices, Crs will increase. As Crs strongly depends on Vds, it is to be expected that paralleled devices will have a poorer frequency response and a poorer linearity.
Thanks, this is what I thought. Now as to the second part, how significant is it? I.e., for the devices we're talking about here, what's the difference in frequency response and distortion (as an estimate, assuming a 25k source impedance from a worst-case 100k pot) from paralleling two lower Idss parts compared to a single higher Idss part?
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Old 6th January 2010, 01:56 PM   #3343
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But linearity of transfer characteristics is much better near to Idss. And even for FB designs there are no stability issues - depends on overall design. If you compare high and low idle, you get both lower distortion and better sound ()at high idle.

Somewhere in this forum someone posted a chart of the ID vs. VGS of the 2SK170BL with 0V < VGS < 0.6V (ID> IDSS). In this case we would have even greater linearity but soon came to me one question: how are the capacitances of fet in this situation?!

eD
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Old 6th January 2010, 02:20 PM   #3344
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Thanks, this is what I thought. Now as to the second part, how significant is it? I.e., for the devices we're talking about here, what's the difference in frequency response and distortion (as an estimate, assuming a 25k source impedance from a worst-case 100k pot) from paralleling two lower Idss parts compared to a single higher Idss part?
I might ask why worry so much about noise if your source is a 100K pot? I thought we were talking about phono front ends.
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Old 6th January 2010, 02:28 PM   #3345
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Thanks, this is what I thought. Now as to the second part, how significant is it? I.e., for the devices we're talking about here, what's the difference in frequency response and distortion (as an estimate, assuming a 25k source impedance from a worst-case 100k pot) from paralleling two lower Idss parts compared to a single higher Idss part?
See attached. As expected (as long as Crss doubles), the 3dB cutoff is about half (from 128KHz down to 67KHz).

Also as expected, distortions are increasing with about the square root of the Crss ratio (here, 2), from 1.5% to 2%. This is for 100mV input and gain as in the attached picture. Idss is about 20mA.

Edit: Of course, green is single JFET, red is two paralleled JFETs, for about the same Idss. Bottom line, John is right but for all the wrong reason. It is the Crss that degrades the parallel JFET configuration, not the (input) Ciss.
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Last edited by syn08; 6th January 2010 at 02:39 PM.
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Old 6th January 2010, 02:46 PM   #3346
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I might ask why worry so much about noise if your source is a 100K pot? I thought we were talking about phono front ends.
John brought up the input pot; the worry was apparently the doubling (which does not seem to be the case) of Cin. That's where I was having trouble understanding.
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Old 6th January 2010, 02:48 PM   #3347
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Also as expected, distortions are increasing with about the square root of the Crss ratio (here, 2), from 1.5% to 2%. This is for 100mV input and gain as in the attached picture. Idss is about 20mA.
Many thanks! How does that scale for a 1mV input, more characteristic of a phono stage. where (as Scott points out) the noise motivates paralleling if selection is impractical?
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Old 6th January 2010, 02:53 PM   #3348
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See attached. As expected (as long as Crss doubles), the 3dB cutoff is about half (from 128KHz down to 67KHz).

Also as expected, distortions are increasing with about the square root of the Crss ratio (here, 2), from 1.5% to 2%. This is for 100mV input and gain as in the attached picture. Idss is about 20mA.

Edit: Of course, green is single JFET, red is two paralleled JFETs, for about the same Idss. Bottom line, John is right but for all the wrong reason. It is the Crss that degrades the parallel JFET configuration, not the (input) Ciss.
Yet, in your phono stage you have 4 JFETs in parallel.
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Old 6th January 2010, 02:57 PM   #3349
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Many thanks! How does that scale for a 1mV input, more characteristic of a phono stage. where (as Scott points out) the noise motivates paralleling if selection is impractical?
For a phono stage, it doesn't make sense to consider a 25K source impedance. For a realistic 50ohm @ 20KHz MC impedance, the distortion gap widens to about 3:1, but numbers are already low (0.01% to 0.03%). Bottom line, for MC preamps, paralleling JFETs has practically no impact on distortions and bandwidth (because of the low source impedance).

EDIT: for MM, the situation is significantly different, both because of larger input signal (2.5...5mV) and large equivalent source impedance @ 20KHz.

Last edited by syn08; 6th January 2010 at 03:04 PM.
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Old 6th January 2010, 03:03 PM   #3350
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Yet, in your phono stage you have 4 JFETs in parallel.
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