I've breadboarded Treble part of the LFO to try some ideas (acceleration time control knob), but the circuit does not oscillate and when connecting PIN 4 of the CA3280 to the zener diode, negative supply voltage drops from -15V to -9.6V??
Oscilloscope also shows no oscillation in the circuitry at all. The only thing that differs from original schematics is 2N3904 and 2N3906 in place of BC550/560 and 2 JRC4558 dual opamps instead of RC4136s in schematics... Any ideas?
Oscilloscope also shows no oscillation in the circuitry at all. The only thing that differs from original schematics is 2N3904 and 2N3906 in place of BC550/560 and 2 JRC4558 dual opamps instead of RC4136s in schematics... Any ideas?
An externally hosted image should be here but it was not working when we last tested it.
In such a case I measure the voltage at each input- and output pins of all OP-amps /OTA and EBC of the bjts inside this part of the circuit and draw them into a copy of the circuit diagram.
While doing this you may find some "unlogical" value - track this to find the error(s).
You are welcome to upload the "decorated" circuit diagram for further investigations by me.
The zener is indeed a neg supply voltage reducer to keep the neg output swing of OTA several volts above -15V rail. Otherwise the input voltage range of RC4136 may be exceeded, producing phase reversal at the output - these OPAs do not provide rail-to-rail-inputs.
I think your replacements are ok so far.
While doing this you may find some "unlogical" value - track this to find the error(s).
You are welcome to upload the "decorated" circuit diagram for further investigations by me.
The zener is indeed a neg supply voltage reducer to keep the neg output swing of OTA several volts above -15V rail. Otherwise the input voltage range of RC4136 may be exceeded, producing phase reversal at the output - these OPAs do not provide rail-to-rail-inputs.
I think your replacements are ok so far.
Last edited:
Thank you for your help Voltwide! Ok, here it is.
Regarding power supply: I used 9VDC (500mA) regulated power supply into LT1054CN (100mA) voltage doubler/charge pump to get +15.5 VDC and further into another LT1054CN circuit to get inverted -15.5 VDC. Voltages at all IC power pins stay +15V/-15V untill I connect PIN 4 of the OTA to zener ( to -15V supply - when complete supply voltages drop to +10V/-9.6V...
Regarding power supply: I used 9VDC (500mA) regulated power supply into LT1054CN (100mA) voltage doubler/charge pump to get +15.5 VDC and further into another LT1054CN circuit to get inverted -15.5 VDC. Voltages at all IC power pins stay +15V/-15V untill I connect PIN 4 of the OTA to zener ( to -15V supply - when complete supply voltages drop to +10V/-9.6V...
An externally hosted image should be here but it was not working when we last tested it.
There must be something faulty about the OTAs.
Have look at pnp-Transistor Q002 on top. Its emitter at -2,08V.
Emitter current is constant given by 2,08V/R039+R199+R192. This constant current should be fed into OTA control inputs through R188 und R189.
The base is -2,7V - thats fine, this is the BE difference one should expect.
But collector voltage is -2,08V: null voltage drop along CE!
This is a strong indication for Null collector current flowing at all!
Next question: Where does emitter current end up with no collector current?
It flows through the base to OPAout (pin3).
In any case you have to trace why collector current of Q002 is disrupted.
Another question arises considering D007. You feed in -15V into the 6V2-Zener, at the cathode you measure -3V. Along the 6V2 is a voltage drop of 12V? This is the next question...
Later on I will look again and maybe I found more....
Have look at pnp-Transistor Q002 on top. Its emitter at -2,08V.
Emitter current is constant given by 2,08V/R039+R199+R192. This constant current should be fed into OTA control inputs through R188 und R189.
The base is -2,7V - thats fine, this is the BE difference one should expect.
But collector voltage is -2,08V: null voltage drop along CE!
This is a strong indication for Null collector current flowing at all!
Next question: Where does emitter current end up with no collector current?
It flows through the base to OPAout (pin3).
In any case you have to trace why collector current of Q002 is disrupted.
Another question arises considering D007. You feed in -15V into the 6V2-Zener, at the cathode you measure -3V. Along the 6V2 is a voltage drop of 12V? This is the next question...
Later on I will look again and maybe I found more....
Well, after I apply -15V to the anode of the zener diode the voltage at anode drops to -9.5V and -3V at cathode (PIN 4) and positive power supply also drops from +15V to +10V. My guess was also the OTA fault, although I swapped two of them. But I bought it on ebay (China made, unused) it could easily a cat in the sack
...Oooops - I presume 100mA should be fine, but I can not provide exact numbers.
Considering the treble control generator alone, 20mA should do.
it seems its impossible to get a working CA3280 so I'm thinking of using some alternative LFOs that give sine and cosine outputs...
Since I didn't have chance to scope the working LFO circuitry, could you please explain how each segment of the LFO works, voltwide? Is there a way to 'bypass' CA3280 circuitry?
Since I didn't have chance to scope the working LFO circuitry, could you please explain how each segment of the LFO works, voltwide? Is there a way to 'bypass' CA3280 circuitry?
An externally hosted image should be here but it was not working when we last tested it.
This circuitry is just on analague solution, many others are possible.
What it does -
The current outputs of OTA feed an integrating capacitor in a triangle low frequency generator.
The amplitude of output current and hence triangle frequency is proportional to the control current applied to bias input of OTA.
The square voltage at +/- inputs overdrives the OTA and thus simply switches polarity of output current, yielding symmetrical ramp-up and ramp down triangle.
This frequency of the triangle generator is controlled by the speed control circuit
- a small current for low frequency (slow speed)
- a bigger current for high frequency (fast speed)
Additionally, switching control current and hence speed is delayed by an integrator or low pass to simulate inertia of the mechanical system.
Obviously nowadays there are myriads of possible solutions to generate such signal.
On the other hand I wonder that replacements like LM13600 from NS are not available any more?
What it does -
The current outputs of OTA feed an integrating capacitor in a triangle low frequency generator.
The amplitude of output current and hence triangle frequency is proportional to the control current applied to bias input of OTA.
The square voltage at +/- inputs overdrives the OTA and thus simply switches polarity of output current, yielding symmetrical ramp-up and ramp down triangle.
This frequency of the triangle generator is controlled by the speed control circuit
- a small current for low frequency (slow speed)
- a bigger current for high frequency (fast speed)
Additionally, switching control current and hence speed is delayed by an integrator or low pass to simulate inertia of the mechanical system.
Obviously nowadays there are myriads of possible solutions to generate such signal.
On the other hand I wonder that replacements like LM13600 from NS are not available any more?
Last edited:
The blue circle:
on the right you find some special circuitry around the antique CA3130. This is a one of two master clocks for the BBDs . This is a sawtooth generator with constant slew rate but variable level, controlled by preceding pnp-buffer transistor. With increasing voltage at the base of that pnp, the level of sawtooth rises. With the slew rate held constant the cycle increases linearly with control voltage. And so this clock circuit generates a proportional delay (voltage controlled delay) in contrast to a VCO that generates a proportional frequency.
On the left side there is one OTA-segment, its current output terminated with a load resistor and buffered by an OPA-buffer.
This forms a current controlled gain stage, its output is fed into the VCD through another OPA.
The pink circuit obviously contains the other VCD.
on the right you find some special circuitry around the antique CA3130. This is a one of two master clocks for the BBDs . This is a sawtooth generator with constant slew rate but variable level, controlled by preceding pnp-buffer transistor. With increasing voltage at the base of that pnp, the level of sawtooth rises. With the slew rate held constant the cycle increases linearly with control voltage. And so this clock circuit generates a proportional delay (voltage controlled delay) in contrast to a VCO that generates a proportional frequency.
On the left side there is one OTA-segment, its current output terminated with a load resistor and buffered by an OPA-buffer.
This forms a current controlled gain stage, its output is fed into the VCD through another OPA.
The pink circuit obviously contains the other VCD.
Nasty!! Thanks for the explanation. I hope now I have enough bits to try the modification! If I succeed, I'll offer it as a DIY project. I've already powdercoated chasis and etched the PCB based on your pdf file but will have to do some mods to it .The plan is to build the same looking rack mount unit. I might have some more questions for you on the way Voltwide, hope I won't be too boring!
.The plan is to build the same looking rack mount unit. I might have some more questions for you on the way Voltwide, hope I won't be too boring!