(Mic+)preamp+converter - Grand piano recordings

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I've listened to your tracks listed in post #1. They are pretty good. The players are excellent.
Your background noise is non-existent in 2014.

You are not hearing any people because we were alone in the room!! :D

All other background noise were filtered in Adobe Audition. Ms Chancon's ears for any change in the original sound she intended is absolutely sharp, so we had to go several small incremental runs on noise filtering. I also got satisfied with the results.

But I have used the same Zoom H4n for all of those 4 videos from OP.

I also listened to the Chopin Fantasy recorded by Ms chacon in 2013. The 2014 recordings are a major improvement. The 2013 track has distorted piano tone, plus a lot of crowd noise. The Chopin piece does go up the keyboard to nearly the top, so that mike set doesn't really supress the top frequencies like a voice mike would, but all frequencies were somewhat distorted.

You mean this, right:
https://www.youtube.com/watch?v=NBVrFrJYgN0

Well, you won't believe if I told you, but that was an adventure. It was my first time I ever recorded anything from her, and we barely had the time to talk before the concert. So that sound and footage came from a single Canon HG20, about 25 meters away, crappy theater, diagonally placed, handholding (tripod wouldn't fit amongst all the people). There were no mic, just the stereo from the camera! So it explains the distortion.

No wonder the other results got better...


I heard no crowd noise in the 2014 tracks. I suppose your 2014 mike set are cardioids?

Just the Zoom H4n. Two cardioid mics, XY.

Zoom H4n Review

The problem may be that the mixer (preamp?) gain is up too high, to allow the electronics to reproduce the piano attack for the A/D converter. Or perhaps that mike brand compresses volume when it is loud - I don't know.

Well, I don't think it was a too high gain. Before starting, I asked her to play some ff sections of the score, and asked her "not to spare her fingers":D. Still added a few headroom dB's. During edition, I had no indication of clipping whatsoever. Probably it was the overall quality of the H4n. Although it may be a nice bang for the buck, it is surely limited against a grand piano.

I'll try to put a recording on pianostreet in the next week to see if the pings are better from my piano/setup(KSM27) than what you've got. KET recordings are better, I believe.

I'd love to hear that, let me know!

Best of luck in improving your art.

Thanks!
 
If you want the best possible quality, in my opinion, the decimation filter of the AT1201 leaves room for improvement and experimentation. At single rate, the passband does not extend to the usual 0.45 fs and none of the built-in filters completely prevent aliasing. You could solve that by using the multibit modulator output and hooking it up to an FPGA board that runs your own filter. Maybe it's also possible to capture the multibit modulator output and doing the decimation afterwards (I haven't a clue how, though).

By the way, how do you intend to get the data onto the SD card?

If you add any digital circuitry to the circuit, please make sure that clock harmonics do not get within audible distance of odd multiples of half the sigma-delta modulator sample rate. Sigma-delta's are often particularly sensitive to interference near odd multiples of half their sample rate, because this interference can produce sum and difference frequencies with idle tones near half the sigma-delta sample rate. If you don't mind making the thing somewhat heavier, it could be a good idea to use separate shielded boxes for the microphone preamplifier, the ADC and any digital stuff you may need.

The microphone you referred to in the first post needs 48 V +/- 4 V phantom supply, as do most professional condenser microphones. Click on "Downloads" and scroll to the last page of the user manual and you'll see.
 
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Well, I don't think it was a too high gain. Before starting, I asked her to play some ff sections of the score, and asked her "not to spare her fingers":D. Still added a few headroom dB's. During edition, I had no indication of clipping whatsoever.
I've little to add: I've been sick and stretched very thinly since.

Except that I was just listening to a podcast on recording which reminded me it is possible to clip the microphone capsule. Perhaps not relevant here (I did mention I'm spread a little thinly :hypno1:)

Except also that I'm very much enjoying your recordings.
 
If you want the best possible quality, <snip>

Hello MarcelvdG. I am very sorry for the so late response. I missed your replies completely.

Well, after quite some months, the AT1201 + THAT1580+THAT5171 finally got here.

I spent a lot of time getting deep about X2Y caps. Also ordered a handful of them, so I can test and measure their outcomes in our application.

It all started when I saw the input RF filters on the THAT5171 datasheet (pg 9):

An externally hosted image should be here but it was not working when we last tested it.


I got in touch with THAT, asking about their calculation for those values and some real world measurements. Also told them I was considering trying the X2Y caps for those filters, since have some of the greatest characteristics one can desire for those filters: tight capacitance match between the line to ground caps, low ESL and nearly no degradation over time (for the NP0 ones, just like the standard ceramic NP0) or a matched aging for the X7R grade.

That should aim at not degrading CMRR, as well as keeping everything balanced. (at least from the filter's perspective)

So here I quote the reply from THAT:

"Our original network with discrete caps was chosen to minimize the sensitivity of high-frequency CMRR to mismatch of the capacitors but we don't have any data on how well they perform for EMI suppression at various frequencies. We are recently seeing how important RFI suppression is, with more WiFi, Bluetooth, etc. devices are in close contact with audio equipment. The use of these X2Y caps along with common-mode chokes on the input are becoming much more common.
We have definitely seen the effects of rectification of RFI by the large input transistors in our preamp ICs, and we have begun investigating how best to prevent this. We don't have any quantitative data or conclusions at this time."

It seems like a good topic to pursue. Although I am pretty confident about the (purely) electrical benefits, I am not sure about the possible sonic end benefits. But then, we can consider a worst case scenario, in which the mic is near a significant RF source and filtering is not adequate. Far from snake's oil, or acting as to improve audio, it could be a decent precaution, aiming at avoiding distortion in real world cases.

I also got in touch with X2Y, and they explained about the different groundings when you are using X2Y caps as standard decoupling caps or as diff. + CM input cap.

Just to name a few references, if anyone is interested:

X2Y Attenuators - Publications (various applications, including decoupling, EMI suppression, filtering, motors (DC) and real tests)

Page 1 (C) 2014 X2Y Technology Presentation – May ppt download (great images showing some differences between standard MLCC caps. Also highlights some of the most desirable feature of X2Y caps: low inductance and attenuation of EMI because of opposing internal current flow. Common mode and diff. scenarios, and mesaurements)

http://www.x2y.com/publications/emi/nov27-02.pdf (basic structure, impedance, some frequency characterization, noise suppression and EMI, actual measurements)

http://www.x2y.com/publications/decoupling/jun21-06.pdf (Freescale. Great presentation, best layout practices, real applications, a bit of circuit behavior on PCBs)

If you want the best possible quality, in my opinion, the decimation filter of the AT1201 leaves room for improvement and experimentation. At single rate, the passband does not extend to the usual 0.45 fs and none of the built-in filters completely prevent aliasing. You could solve that by using the multibit modulator output and hooking it up to an FPGA board that runs your own filter. Maybe it's also possible to capture the multibit modulator output and doing the decimation afterwards (I haven't a clue how, though).

That is interesting. Could you elaborate a bit more on the AT1201 limitations? I will work with double-speed 96 kHz, and from the datasheet, here is the frequency response:

An externally hosted image should be here but it was not working when we last tested it.

An externally hosted image should be here but it was not working when we last tested it.


That seems to go flat until 0.45 fs. Are you referring to the stop band oscillation?

An externally hosted image should be here but it was not working when we last tested it.


If yes, then we are talking about a -120dB signal folding back. And the input signal is, of course, band limited. OTOH, the graph doesn't show what happens after fs.
I was also wondering about the AAF. Could use some suggestion, any particular practice in audio? I would start with a standard 2 pole Butterworth, flat until 20 kHz (-3dB at 44 kHz):

An externally hosted image should be here but it was not working when we last tested it.


But then the phase behaves like:

An externally hosted image should be here but it was not working when we last tested it.


How important in audio is that phase response? Would a linear phase Bessel be justified?

So a back of envelope math. At 0.45 * fs , we have 43,2 kHz, so just about -3dB. Therefore, your concern is the possible aliasing starting from ~ 44 kHz?
Could you show me if I am missing something?


By the way, how do you intend to get the data onto the SD card?

Well so far I am not much of an FPGA guy myself. I am considering a PIC, maybe 18 series, maybe 24. It would be responsible for getting the data onto the SD card, as well as communicating with the THAT chips and user interface. Not sure about what display capabilities it should have. Fancy displays can easily need a dedicated processor. Let's see...

BTW, thanks for the digital circuitry tips! I certainly don't mind making it a bit heavier for proper separation and shielding.


The microphone you referred to in the first post needs 48 V +/- 4 V phantom supply, as do most professional condenser microphones. Click on "Downloads" and scroll to the last page of the user manual and you'll see.

You are right! And thinking about it, it should be phantom power ready anyway. Lots of capsules need it.

THAT also has some nice suggestions for typical phantom power supplies.
 
I think it is definitely a good idea to include an RF input filter - it would be a shame to hear the typical interference caused by the envelope of a cell phone signal in a live recording, just because someone put his or her phone in silent mode rather than switched off completely. Feedthrough filters can also be very effective at high frequencies, especially when you use shielded boxes.

Analogue anti-alias or anti-imaging filters used with oversampled converters are usually of a type with nearly linear phase response, such as Bessel filters or equiripple linear phase filters. I believe this started in the early 1980's, when Philips successfully marketed their phase-linear CD players, but it also makes sense technically to strive for a linear phase response when there is no urgent reason to do otherwise. The passband droop of these filters can easily be corrected for in the digital filtering, provided that the digital and analogue filter are designed by the same person or by persons who interact with each other. An interesting alternative for a Bessel or equiripple linear phase filter is the transitional Gaussian-Chebyshev filter invented by DeVerl S. Humpherys; it combines a good passband phase response with a steep transition band magnitude response. (See DeVerl S. Humpherys, "Equiripple network approximations using iteration techniques", Proceedings of the National Electronics Conference, vol. 20, 1964, pages 753...758 or DeVerl S. Humpherys, The analysis, design and synthesis of electrical filters, Prentice-Hall, Englewood Cliffs, N. J., 1970.)

Mind you, the output impedance of the filter may affect the performance of the ADC - and I mean the output impedance up to quite high frequencies when the ADC is a switched-capacitor circuit that needs to settle accurately within one clock period. I would be inclined to follow the recommendations of Arda Technologies to the letter for the circuit that directly drives the ADC, and maybe put some extra filter stage in front of it if I wanted to tweak the filter response. The analogue filter is allowed to have a quite wide transition band, because it only needs to reject signals above 12.288 MHz - 48 kHz = 12.24 MHz.

Regarding the digital filtering, it could be that I think too logically or too strictly (I usually do), but this is how I see it:

From Shannon's sampling theorem, a 48 kHz sample rate is theoretically enough to reproduce all signal frequencies up to 24 kHz correctly. As practical anti-alias and reconstruction filters need a transition band, in practice you can reproduce everything up to 21.6 kHz properly if the transition band starts at 0.45 fs.

Still, you choose a sample rate of 96 kHz, so apparently you care about what happens above 21.6 kHz. There can be many reasons for that - for example, you may have read the 1990's article where the electroencephalogram of Japanese gamelan players was monitored while they were listening to gamelan music band limited and not band limited to 26 kHz (Tsutomu Oohashi, Emi Nishina, Norie Kawai, Yoshitaka Fuwamoto and Hiroshi Imai, "High-frequency sound above the audible range affects brain electric activity and sound perception", Audio Engineering Society preprint 3207, presented at the 91st Convention, October 1991), or you may agree with Hans van Maanen's arguments for minimizing ringing above 20 kHz (Hans van Maanen, "On the audibility of "high resolution" digital audio formats and how to test this", Linear Audio, vol. 5, April 2013, pages 57...76), or you may also want your dog to enjoy the recordings (for cats - at least for young cats with no hearing impairment - 96 kHz sample rate doesn't suffice, you would need at least 192 kHz). In any case, you want to reproduce sound above 21.6 kHz.

Looking at the double-rate anti-alias filter plots from the AT1201 datasheet, the stop band only starts at 0.7 fs. This means that from 1 fs - 0.7 fs = 0.3 fs onwards, the signal spectrum can be polluted with aliases. That's 28.8 kHz at 96 kHz sample rate, while normally 96 kHz sample rate would allow proper reproduction of anything up to 43.2 kHz (taking 0.45 fs as transition band start). So the question is: do you care about the part between 28.8 kHz and 43.2 kHz? If so, then you need a better anti-alias filter.

Personally I'm in favour of letting the transition band stop at 0.5 fs, so you only get bandwidth limitations and no aliasing at all (except for the inevitable aliasing due to finite stop band rejection). That is not a popular point of view under digital audio chip manufacturers, because filters with a wider transition band are much cheaper.

Some people are in favour of smooth filtering rather than steep filtering to reduce pre-ringing. The pre-ringing of an ideal 21.6 kHz low-pass filter (that is, neglecting the passband ripple for the moment) consists entirely of frequency components of 21.6 kHz and higher. If you believe these to be audible (at least when heard in combination with the rest of the signal), it again doesn't make sense to allow aliases just above 21.6 kHz.

So the two questions are:
Do you care about signal frequencies above 28.8 kHz?
Do you want a flat response up to as high a frequency as possible, or rather minimize pre- and post-ringing?

The nice thing about FPGA implementations is that you can experiment with these things as much as you like.

On top of that there is the pre-echo associated with the passband ripple. According to an article written by R. Lagadec and T. G. Stockham (Dispersive models for A-to-D and D-to-A conversion systems, AES preprint 2097, March 1984) the passband ripple of +0/-0.015 dB should correspond to a pre- and post-echo of about -67.3 dB - at least if the filter were a symmetrical FIR filter, Figure 18 of the datasheet shows that it is not symmetrical. In any case, -67.3 dB is already pretty good compared to most digital audio chips, but with an FPGA implementation you can easily make it even better.

I'm not a digital expert at all, but I did study various digital FIR filter types and did experiment with FPGA boards when I was designing my own hobby DAC. If you PM me I can send you some information to help you get started.
 
Assuming ideal components, including an ideal op-amp, the input filter recommended in the datasheet of the AT1201 is a second-order low-pass filter with f0 ~= 252307 Hz and Q ~= 0.5037887 if I did my calculations correctly. It could be that in reality the phase shift of the op-amp increases Q somewhat, at 1/sqrt(3) ~= 0.57735 it would turn into a second-order Bessel filter.

The filter in the application note is very similar, although the f0 is slightly higher. The text of the application note claims that it's a first-order filter with 120 kHz cut-off, though.

I had hoped to find some information on why they recommend this specific type of filter, but no such luck. It could be that they simply like the good phase and step responses, but it could also be that the slow roll-off compensates for out-of-band peaking of the sigma-delta. The frequency response graphs in the datasheet are all for the digital filters only, it doesn't say anything about the signal transfer function of the sigma-delta.
 
I also did some calculations on a possible alternative decimation chain. You have to decimate 128 times. The first factor of 16 could be done with a sixth-order CIC filter, then you could insert a simple equalizer circuit with a -beta, 1+2beta, -beta impulse response and then two serious FIR filters, one that decimates four times and one for the last factor of two. By giving the last filter two alternative coefficient sets, you could choose between a steep and a smooth (apodizing) response. By tweaking the parameter beta of the equalizer, you can rather nicely correct for the roll-off of the CIC filter and (if necessary) of the analogue filter.
 
Hi Marcel,

Just posting to say I value your inputs a lot! Sorry for my delays, truth is I have been actually drowned in studying! You have mentioned some filters I haven't seen, and other aspects of your assessment as well. I am just finding a better basis for replying.

Also some work trips have taken some time. Please hold a bit, if you may!

Just PM you about that FPGA stuff! ;)
 
Analogue anti-alias or anti-imaging filters used with oversampled converters are usually of a type with nearly linear phase response, such as Bessel filters or equiripple linear phase filters. I believe this started in the early 1980's, when Philips successfully marketed their phase-linear CD players, but it also makes sense technically to strive for a linear phase response when there is no urgent reason to do otherwise. The passband droop of these filters can easily be corrected for in the digital filtering, provided that the digital and analogue filter are designed by the same person or by persons who interact with each other. An interesting alternative for a Bessel or equiripple linear phase filter is the transitional Gaussian-Chebyshev filter invented by DeVerl S. Humpherys; it combines a good passband phase response with a steep transition band magnitude response. (See DeVerl S. Humpherys, "Equiripple network approximations using iteration techniques", Proceedings of the National Electronics Conference, vol. 20, 1964, pages 753...758 or DeVerl S. Humpherys, The analysis, design and synthesis of electrical filters, Prentice-Hall, Englewood Cliffs, N. J., 1970.)

I tried to find the paper you mentioned, and also the Proceedings, but I could not find any online resource. Any link for the abstract? Under the University access, I might try my luck and see if I have full access.

Also coudn't find Humpherys's book, but a few amazon links.

I did find some information on transitional Gaussian-Chebyshev, however, on Walter Jung's Op Amp Applications Handbook, Elsevier 2005 Chapter 5: Analog Filters, pg 327. But he just works on the definition and tabulates the Gaussian to 6dB and Gaussian do 12dB. Jung also works on design examples - even a CD quality D/A reconstruction filter, but he chooses a 7th order Bessel. On a side note, the final results seem interesting! Figure 5-110, page 413.

As I would like to keep an open mind, get to know about as many alternatives as possible, simulate and implement some of the choices, I'd like to ask if you or anyone knows if there is a preferred AFE filter topology/implementation on the high end industry. Or if there is no such thing...

Mind you, the output impedance of the filter may affect the performance of the ADC - and I mean the output impedance up to quite high frequencies when the ADC is a switched-capacitor circuit that needs to settle accurately within one clock period. I would be inclined to follow the recommendations of Arda Technologies to the letter for the circuit that directly drives the ADC, and maybe put some extra filter stage in front of it if I wanted to tweak the filter response.

Absolutely! There is a reference circuit on the App note AN-AT1201-1 Design and Layout Guidelines for the AT1201:

View attachment Application Note - Design and Layout Guidelines for the AT1201 - at1201-an-1.pdf


I took quite some time over these days on Figure 5, pg 5, that is the suggested input network for the AT1201:

An externally hosted image should be here but it was not working when we last tested it.


Some questions and notes I took here.

1) BUFREF is generated internally (pg. 5, first paragraph). I've worked with high performance differential inputs ADCs that generate their own (ideal) CM voltage to the driving circuit. On the ADC driver op amp side, traditionally a fully differential amplifier, there is an CM input pin that sets the CM output voltage. Leave the CM input pin unconnected, and the amplifier internally sets the CM voltage to mid-supply. This is also the case of the OPA1632.

I do not understand what is happening with the pins BUFREF, REFPR/REFPL and CMREF, as well as the circuitry around it. First, a peek on the datasheet:

An externally hosted image should be here but it was not working when we last tested it.


I understand that BUFREF is an internally generated voltage that drives the VCM of the ADC inputs driver op amp. It is specified as an output pin and can be left "as is", driving the input VCM of the op amp directly or simply buffered. It can also be overridden by an external voltage reference. The REFPR and REFPL represent, as usual in ADCs, the reference against which the input signal will be compared. Their nominal value is 4.8V, so the BUFREF is half of that. REFP can also be overridden, and in such case one should also provide an external voltage to BUFREF that is half the REFP voltage if the highest symmetrical dynamic range is to be achieved. So far, so good.

But how come the CMREF nominal voltage is 2.5V and the BUFREF nominal voltage is 2.4V? Shouldn't their nominal values be the same?

To make matters a bit more confusing, there seems to be 2 different approaches to CMREF pins.

In the AT1201 datasheet, the CMREF pins are described as analog outputs common-mode voltage, internally generated reference, ties to capacitor:

An externally hosted image should be here but it was not working when we last tested it.


And the app note says the same, and there is only this tie to capacitor option for these pins. (figs 12 and 13, pg 9)

But the evk circuit connects them to a voltage divider coming from VA, that is +5V. The resistors seem to be there for experimentation purposes, since they are described as NS:

An externally hosted image should be here but it was not working when we last tested it.


Does everybody agree that those footprints should not be populated?

BTW here is the EVK guide, since it is not freely available for download. I've split it in two because of forum restrictions:

View attachment at1201evk-ugpart1.pdf
View attachment at1201evk-ugpart2.pdf

You can check the board here AT1201EVK - AT1201 Evaluation Board (Master Part).

As a side note, it has not been easy to find documents on nearly anything from Arda. Last I heard, they were bought by a huge company, but that is completely unofficial. I will try my ways to get in touch with them. I'll gather all the questions first.

Now back to BUFREF. From the app note, pg 5: "BUFREF is an internally generated reference voltage for the buffers driving the analog inputs. Resistors R1 and R2 trim BUFREF to its optimum value, which must be set precisely to 2.4V for the AT1201."

The OPA1632 gain is set to (270+40.2)/910 = 0.34. Considering the +23dbU (~11V) max input signal mentioned on the EVK guide, we have: 0.34 * 10.95V = 3.72V. That is the differential voltage between INxP and INxN. So the total voltage is VCM +- Vdiff/2. That yields 2.4V +- 1.861 = 4.261V and 0.539V

Since the AT1201 min. full scale input voltage is 4.35V (datasheet, pg 6), that is fine. But the OPA1632 VCM is not being driven by 2.4V after that voltage divider.

The voltage divider with the recommended values for R1 and R2 (3k3 and 2k61) alone (without the 1k resistor + BUFREF) results in 2.208 V. Considering the 2.4V at the BUFREF pin, the resulting voltage on the positive terminals of each buffer is 2.322V and the current drawn from the 2.4V is 78µA. That voltage won't ever reach 2.4V, and the current exceeds the 0.01 mA max from the BUFREF pin (sink/source). It also won't reach 2.5V, and either won't match the nominal 2.5V of CMREF.

What is going on?


2) Now disregarding whatever it is I am missing above, and assuming the circuit on Fig. 5 of the app note is right, I frowned upon their reference choice "driving" the BUFREF pin.

It strikes me odd their "+5V regulated" choice, as well as their lack of requirement/information on the external reference.

This is an all important CM buffer reference, so accuracy, precision and stability should be taken seriously. An ADC is just as good as its reference (and power supply), and the same applies to the CM voltage driving the op amp. On the EVK, they really used their analog supply:

An externally hosted image should be here but it was not working when we last tested it.



VA is +5V and comes from an LT1762EMS8-5. That is an LDO. A fine 20 uV RMS low noise LDO, but still an LDO.

The AT1201 SINAD is 105 dB. So its ENOB = (105 - 1.76) / 6.02 = 17.15 bits. In 5V, that is 34.4 uV . I don't think an LDO supplying a variable current for the whole analog circuit fits as a good reference.

I'd rather use a very low noise / stable reference, such as MAX6350CSA+. Here is the datasheet: https://datasheets.maximintegrated.com/en/ds/MAX6325-MAX6350.pdf. In short, it is a 1ppm/°C Max Tempco, 1.5μVp-p Noise (0.1Hz to 10Hz), ±0.02% Initial Accuracy, capable of 15mA (source and sink). A buffer and filter are usually recommended after the reference chip, and naturally the op amp should be DC oriented. As a side note, the MAX60xx family is already buffered inside the chip.

As an alternative, maybe (just maybe) a REF6050.


It could also be used in REFPL and REFPR reference drive circuit (app note, Fig. 8, pg 7), that also oddly calls for a +5V regulated, instead of a reference.


Any other thoughts/objections/opinions here?



3) Next, the input network in fig. 5 (app note), the LPF after the NE5532 is set to 48 Hz, which seems to me as a very high cut off frequency, specially for a 1 pole filter. Any ideas why the cut off frequency is not set to something below 1 Hz? Maybe the reason is that it would require larger capacitance values, and they were concerned about the op amp stability. But that would be a lame excuse, so I don't think it is the case.

Even much better references than "+5V regulated" are filtered at a much lower frequency even for a good true 16 bits system, let alone a 24 bits ADC. For a reference (one out of many), see http://www.ti.com/lit/ug/slau515a/slau515a.pdf

If anyone is interested, I can suggest a handful of books and documents showing how to design a good reference for an ADC system - particularly SAR and sigma-delta.

4) they forgot to close the buffer feedback loop on Fig. 5:

An externally hosted image should be here but it was not working when we last tested it.


Guess that won't work on first try! :)) lol

5) Still on Fig. 5, since we are talking about the holy CM reference for the ADC driver, I just realized that I am tempted to make some real world measurements replacing those 100nF for X2Y ones... Guess I got a taste for those....


6) in the AT1201 datasheet, pg 28, there is a simplified input buffer circuit. There, there is a big chunk of 100 uF caps that are the first thing the input signal sees. Along with the 1k resistor, they make a HPF, I believe mostly for decoupling DC since cut off frequency is 1.59 Hz. These caps are missing on the AN-AT1201-1, Fig. 5 ! It seems like those caps should be there. Agree?

An externally hosted image should be here but it was not working when we last tested it.


The analogue filter is allowed to have a quite wide transition band, because it only needs to reject signals above 12.288 MHz - 48 kHz = 12.24 MHz.

Right. The above simplified input buffer circuit shows the HPF @ 1.6 Hz and the LPF looks like a regular Butterworth, but they made the clever move of splitting the Rf resistor, so the LPF cut off frequency is still 1/[2*pi*(270+R3)*3.9nF]. With the suggested 40.2 ohms value for R3, that is 131.5 kHz.

Checking after writing, they weren't the clever ones! They just used it from the OPA1632 datasheet...

From the datasheet, all that is informed is: "AT1201. The input buffer must be able to drive the switched-capacitor input impedance of the modulator as well as provide anti-aliasing at multiples of the sampling rate, which is nominally 12.288MHz. The circuits shown below achieve both of these goals. Note that feedback capacitor around the operational amplifier should be a C0G type with low voltage coefficient. The inverting buffer configuration is recommended."

The 131.5 KHz cutoff frequency is almost a decade before the nominal 12.288MHz and achieves the goal for the LPF.

One advantage I could spot on splitting the resistors in the FB loop is that there is no need for another series resistor before C1 (or C2, C4, C5).

Which raises the question: since there already a 40.2 ohm resistor in series with the caps, what on earth is that 1 ohm resistor doing there? Maybe it is a room for improving balance/matching, so one can add any other resistor as needed after measurement? Nah, it doen't soudn right. There is no mention to that on the datasheet or app. note.

Here is the simulation of both circuits. Vout represents the circuit with the 1ohm resistor, and Vout2 without it:

An externally hosted image should be here but it was not working when we last tested it.



7) I also did not get why they simply did not choose a more straight forward, "less clever" driver, like the one below:

An externally hosted image should be here but it was not working when we last tested it.


The results are very close to their choice:

An externally hosted image should be here but it was not working when we last tested it.



I don't get why they had the 40.2 resistor in the buffer feedback loop, and the capacitor is differentially set up. I checked on Walt Jung Op Amp Applications Handbook (both chapter 3: Driving ADC inputs and chapter 5: Analog Filters , Douglas Self Small Signal Audio Design, 2nd ed., and Steve Winder Analog and Digital Filter Design 2nd ed., and did not find this construction. This 3.9nF + 40.2 ohms elements on the FB loop are not present on any of the sigma delta drivers I found, ie:

An externally hosted image should be here but it was not working when we last tested it.


Souce: http://www.analog.com/media/en/tech...tes/28715432842357460935458165408691AN388.pdf

I have found, however, this exact technique on the OPA1632 datasheet, Fig 14, pg 13. But they do not elaborate any about it.
Glen Bloou also mentions this OPA1632 circuit as an ADC driver on his Handbook for Sound Engineers, but no extra explanation is found.

I'd appreciate if someone could explain it to me, or suggest any further reference.


8) Obviously, the last caps (C1 - C6) act as an usual charge reservoir to the input caps and its roll off just kicks in much later on the freq. response, as expected.

I am also willing to replace those caps for X2Y ones. The reason being that those are important elements concerning balance. And again the X2Y closed matched properties are beyond the realm of the discrete caps.


9) what are those "pull down like" 3k3 resistors doing there on the OPA1632 output? They are there on the EVK as well. Could anyone elaborate on that?

An externally hosted image should be here but it was not working when we last tested it.
 
Regarding the digital filtering, it could be that I think too logically or too strictly (I usually do), but this is how I see it:

From Shannon's sampling theorem, a 48 kHz sample rate is theoretically enough to reproduce all signal frequencies up to 24 kHz correctly. As practical anti-alias and reconstruction filters need a transition band, in practice you can reproduce everything up to 21.6 kHz properly if the transition band starts at 0.45 fs.

Still, you choose a sample rate of 96 kHz, so apparently you care about what happens above 21.6 kHz. There can be many reasons for that - for example, you may have read the 1990's article where the electroencephalogram of Japanese gamelan players was monitored while they were listening to gamelan music band limited and not band limited to 26 kHz (Tsutomu Oohashi, Emi Nishina, Norie Kawai, Yoshitaka Fuwamoto and Hiroshi Imai, "High-frequency sound above the audible range affects brain electric activity and sound perception", Audio Engineering Society preprint 3207, presented at the 91st Convention, October 1991), or you may agree with Hans van Maanen's arguments for minimizing ringing above 20 kHz (Hans van Maanen, "On the audibility of "high resolution" digital audio formats and how to test this", Linear Audio, vol. 5, April 2013, pages 57...76), or you may also want your dog to enjoy the recordings (for cats - at least for young cats with no hearing impairment - 96 kHz sample rate doesn't suffice, you would need at least 192 kHz). In any case, you want to reproduce sound above 21.6 kHz.

No, I don't. I also take a very logical approach to the whole audio conversion stuff. It is simply data. Being converted by an ADC. And being reproduced latter on. (disregarding any intentional digital processing here) The way I see it, every single piece of consequence of the Shannon's sampling theorem and general data conversion theory applies to any audio signal. And to any other signal as well.

So my approach is to treat the whole thing as I would to any other problem concerning AD conversion, the main frame being: get to know deeply the spectral content of your source(s), condition your signal and band limit it properly, understand the noise, EMI, distortion and clipping throughout the signal chain, be very very careful with your layout, use the proper AD conversion technique to your application. And of course, the details... the details...

I don't care what happens after 20 KHz. And not just that, I realize the troubles that come with coding BW that is not supported by the audio players down the road. Simply put, the listenable portion of the spectrum may get messed (mainly due to intermodulation). Here are some references that I tend to strongly agree with:

24/192 Music Downloads are Very Silly Indeed
http://lavryengineering.com/pdfs/lavry-sampling-oversampling-imaging-aliasing.pdf
http://www.lavryengineering.com/pdfs/lavry-white-paper-the_optimal_sample_rate_for_quality_audio.pdf
http://lavryengineering.com/pdfs/lavry-sampling-theory.pdf
CiteSeerX — Coding High Quality Digital Audio
https://www.soundonsound.com/sound-advice/q-should-i-use-high-sample-rates

So in short, the only reason I am choosing a 96kHz sampling is that it relaxes the requirements on the analog filter. It allows the cut off frequency to be extended and a flatter passband, without the need for higher order filters, that usually mess up with something - group delay, passband ripples, phase distortion. Note that I am not an experienced filter designer, though. Just the basics.

Looking at the double-rate anti-alias filter plots from the AT1201 datasheet, the stop band only starts at 0.7 fs. This means that from 1 fs - 0.7 fs = 0.3 fs onwards, the signal spectrum can be polluted with aliases. That's 28.8 kHz at 96 kHz sample rate, while normally 96 kHz sample rate would allow proper reproduction of anything up to 43.2 kHz (taking 0.45 fs as transition band start). So the question is: do you care about the part between 28.8 kHz and 43.2 kHz? If so, then you need a better anti-alias filter.

No, I would like to have no signal from 20 kHz upward.

Personally I'm in favour of letting the transition band stop at 0.5 fs, so you only get bandwidth limitations and no aliasing at all (except for the inevitable aliasing due to finite stop band rejection). That is not a popular point of view under digital audio chip manufacturers, because filters with a wider transition band are much cheaper.

Some people are in favour of smooth filtering rather than steep filtering to reduce pre-ringing. The pre-ringing of an ideal 21.6 kHz low-pass filter (that is, neglecting the passband ripple for the moment) consists entirely of frequency components of 21.6 kHz and higher. If you believe these to be audible (at least when heard in combination with the rest of the signal), it again doesn't make sense to allow aliases just above 21.6 kHz.

So the two questions are:
Do you care about signal frequencies above 28.8 kHz?
Do you want a flat response up to as high a frequency as possible, or rather minimize pre- and post-ringing?

Truth is that pre- and post-ringing is a subject that I see is important to audio, and I will have to catch up about it. I have no knowledge/experience on that end so far. So I can't give an opinion right now. But I do intend to learn about it so the solution gets truly well done.

So if no physical law forbids it, I am striving for a neutral and flat response from 20 Hz to 20 KHz, no ringing at all. :D Just as the instrument sounded, on the recording spot, capturing the sonic experience. No more.

As a final note, warm, rich, colorful, embodied... that sounds great, but that comes from a particular interpretation of the mind. I'd like to stick to what we can measure and improve objectively, at least for now.
 
If you believe frequencies above 20 kHz to be inaudible under all circumstances, you also don't need to worry about pre-ringing above 20 kHz. Pre-echoes due to passband ripple are a different story.

Using a 96 kHz sample rate will not make life any easier for the analogue anti-alias filter. It will only make life easier for the digital decimation chain. The sigma-delta has a sample rate of 12.288 MHz, so you only need to suppress signals around 12 MHz and higher with your analogue filter. It's the task of the digital decimation filters to suppress the aliases that are generated when the signal gets decimated to 96 kHz or 48 kHz or whatever.
 
Assuming ideal components, including an ideal op-amp, the input filter recommended in the datasheet of the AT1201 is a second-order low-pass filter with f0 ~= 252307 Hz and Q ~= 0.5037887 if I did my calculations correctly. It could be that in reality the phase shift of the op-amp increases Q somewhat, at 1/sqrt(3) ~= 0.57735 it would turn into a second-order Bessel filter.

The filter in the application note is very similar, although the f0 is slightly higher. The text of the application note claims that it's a first-order filter with 120 kHz cut-off, though.

I had hoped to find some information on why they recommend this specific type of filter, but no such luck. It could be that they simply like the good phase and step responses, but it could also be that the slow roll-off compensates for out-of-band peaking of the sigma-delta. The frequency response graphs in the datasheet are all for the digital filters only, it doesn't say anything about the signal transfer function of the sigma-delta.

Marcel, I could not follow that f0. Would you detail you calculation?

What I figured out is that they are probably referring to the driver response alone, excluding the reservoir C1-C3 cap + 1 ohm resistor.

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On the circuit on the right, just the driver, Vout3 is -30.17 dB @ ~ 1kHz, about the center of the passband (log scale, of course). I had just 2 markers, so I couldn't show it. Vout 3 has a -3dB cut off frequency @ 116.2 kHz.

It makes sense, if you redraw the circuit without taking the into account the R3 (and R4) splitting the FB loop, it gets to an usual 1 pole filter:

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1 pole for the HP and other for the LP.

I also still don't get why they chose that setup that is first present on the OPA1632 datasheet (please refer to #33). It would be nice to have this driver circuit completely understood.
 
If you believe frequencies above 20 kHz to be inaudible under all circumstances, you also don't need to worry about pre-ringing above 20 kHz. Pre-echoes due to passband ripple are a different story.

Using a 96 kHz sample rate will not make life any easier for the analogue anti-alias filter. It will only make life easier for the digital decimation chain. The sigma-delta has a sample rate of 12.288 MHz, so you only need to suppress signals around 12 MHz and higher with your analogue filter. It's the task of the digital decimation filters to suppress the aliases that are generated when the signal gets decimated to 96 kHz or 48 kHz or whatever.

Yes, you are absolutely right! Bad writing of mine... :rolleyes: I should have written "...choosing a 96kHz sampling is that it relaxes the requirements on the digital filter. "

As you said, it will be great to experiment with different digital filters and see the results. If the results are optimal down with fs = 48 kHz, that seems fine for me from the reconstruction perspective, ie, BW up to 20KHz. If a smoother filter will bring any benefit, well then I don't see why not call the trade, as long as the final signal is band-limited to 20kHz.

How sensible does that sound to you?
 
But how come the CMREF nominal voltage is 2.5V and the BUFREF nominal voltage is 2.4V? Shouldn't their nominal values be the same?

Not necessarily; I get the impression that CMREFL and CMREFR are decoupling pins for common-mode voltages for internal circuitry. It could very well be that the internal circuitry has maximum headroom when the common mode is halfway the supply rather than halfway the reference voltage.

You probably need details of the internal circuitry to fully understand what is going on here, which you'll never get because of company confidentiality.

To make matters a bit more confusing, there seems to be 2 different approaches to CMREF pins.

In the AT1201 datasheet, the CMREF pins are described as analog outputs common-mode voltage, internally generated reference, ties to capacitor:

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And the app note says the same, and there is only this tie to capacitor option for these pins. (figs 12 and 13, pg 9)

But the evk circuit connects them to a voltage divider coming from VA, that is +5V. The resistors seem to be there for experimentation purposes, since they are described as NS:

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Does everybody agree that those footprints should not be populated?

I certainly agree that they should not be populated. It looks like ARDA technologies used a chip validation board as customer evaluation kit. For debugging a chip one would normally reserve space on the board for anything one can think of that might come in handy to find out what is happening on the chip (as long as it doesn't mess up the board layout so much that it could harm the performance). For a customer evaluation kit one would normally throw away all this debugging stuff.

This might also explain the weird 1 ohm resistors. They are very handy to measure currents; connect a differential probe across the resistor and you can monitor the current.

Now back to BUFREF. From the app note, pg 5: "BUFREF is an internally generated reference voltage for the buffers driving the analog inputs. Resistors R1 and R2 trim BUFREF to its optimum value, which must be set precisely to 2.4V for the AT1201."

The OPA1632 gain is set to (270+40.2)/910 = 0.34. Considering the +23dbU (~11V) max input signal mentioned on the EVK guide, we have: 0.34 * 10.95V = 3.72V. That is the differential voltage between INxP and INxN. So the total voltage is VCM +- Vdiff/2. That yields 2.4V +- 1.861 = 4.261V and 0.539V

Since the AT1201 min. full scale input voltage is 4.35V (datasheet, pg 6), that is fine. But the OPA1632 VCM is not being driven by 2.4V after that voltage divider.

The voltage divider with the recommended values for R1 and R2 (3k3 and 2k61) alone (without the 1k resistor + BUFREF) results in 2.208 V. Considering the 2.4V at the BUFREF pin, the resulting voltage on the positive terminals of each buffer is 2.322V and the current drawn from the 2.4V is 78µA. That voltage won't ever reach 2.4V, and the current exceeds the 0.01 mA max from the BUFREF pin (sink/source). It also won't reach 2.5V, and either won't match the nominal 2.5V of CMREF.

What is going on?

Did you take into account the 14.5 kohm output resistance of BUFREF? (Datasheet page 23.)

Wild guess: maybe during validation they found that the chip works better with a slightly lower common-mode reference, so they added the stupid resistor circuit?

2) Now disregarding whatever it is I am missing above, and assuming the circuit on Fig. 5 of the app note is right, I frowned upon their reference choice "driving" the BUFREF pin.

It strikes me odd their "+5V regulated" choice, as well as their lack of requirement/information on the external reference.

This is an all important CM buffer reference, so accuracy, precision and stability should be taken seriously. An ADC is just as good as its reference (and power supply), and the same applies to the CM voltage driving the op amp. On the EVK, they really used their analog supply:

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VA is +5V and comes from an LT1762EMS8-5. That is an LDO. A fine 20 uV RMS low noise LDO, but still an LDO.

The AT1201 SINAD is 105 dB. So its ENOB = (105 - 1.76) / 6.02 = 17.15 bits. In 5V, that is 34.4 uV . I don't think an LDO supplying a variable current for the whole analog circuit fits as a good reference.

I'd rather use a very low noise / stable reference, such as MAX6350CSA+. Here is the datasheet: https://datasheets.maximintegrated.com/en/ds/MAX6325-MAX6350.pdf. In short, it is a 1ppm/°C Max Tempco, 1.5μVp-p Noise (0.1Hz to 10Hz), ±0.02% Initial Accuracy, capable of 15mA (source and sink). A buffer and filter are usually recommended after the reference chip, and naturally the op amp should be DC oriented. As a side note, the MAX60xx family is already buffered inside the chip.

As an alternative, maybe (just maybe) a REF6050.


It could also be used in REFPL and REFPR reference drive circuit (app note, Fig. 8, pg 7), that also oddly calls for a +5V regulated, instead of a reference.


Any other thoughts/objections/opinions here?
What you write sounds perfectly logical. Of course there is some common-mode rejection, but even then, you would like a reasonably clean CM reference.

3) Next, the input network in fig. 5 (app note), the LPF after the NE5532 is set to 48 Hz, which seems to me as a very high cut off frequency, specially for a 1 pole filter. Any ideas why the cut off frequency is not set to something below 1 Hz? Maybe the reason is that it would require larger capacitance values, and they were concerned about the op amp stability. But that would be a lame excuse, so I don't think it is the case.
It's even weirder on the evaluation kit schematic (page 15), where the 100 ohm is included in the feedback loop around the LM4562 and hence doesn't filter at all, only limits the start-up current and possibly causes instability.

5) Still on Fig. 5, since we are talking about the holy CM reference for the ADC driver, I just realized that I am tempted to make some real world measurements replacing those 100nF for X2Y ones... Guess I got a taste for those....


6) in the AT1201 datasheet, pg 28, there is a simplified input buffer circuit. There, there is a big chunk of 100 uF caps that are the first thing the input signal sees. Along with the 1k resistor, they make a HPF, I believe mostly for decoupling DC since cut off frequency is 1.59 Hz. These caps are missing on the AN-AT1201-1, Fig. 5 ! It seems like those caps should be there. Agree?

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I guess so. If they are not there, you will get a DC common-mode current flowing into the XLR input, when the signal source has 0 V common-mode output voltage.

The above simplified input buffer circuit shows the HPF @ 1.6 Hz and the LPF looks like a regular Butterworth, but they made the clever move of splitting the Rf resistor, so the LPF cut off frequency is still 1/[2*pi*(270+R3)*3.9nF]. With the suggested 40.2 ohms value for R3, that is 131.5 kHz.

Checking after writing, they weren't the clever ones! They just used it from the OPA1632 datasheet...

I don't agree here. Including the capacitors at the output you get a second-order filter.

From the datasheet, all that is informed is: "AT1201. The input buffer must be able to drive the switched-capacitor input impedance of the modulator as well as provide anti-aliasing at multiples of the sampling rate, which is nominally 12.288MHz. The circuits shown below achieve both of these goals. Note that feedback capacitor around the operational amplifier should be a C0G type with low voltage coefficient. The inverting buffer configuration is recommended."

The 131.5 KHz cutoff frequency is almost a decade before the nominal 12.288MHz and achieves the goal for the LPF.
I guess you mean two decades?

One advantage I could spot on splitting the resistors in the FB loop is that there is no need for another series resistor before C1 (or C2, C4, C5).

Which raises the question: since there already a 40.2 ohm resistor in series with the caps, what on earth is that 1 ohm resistor doing there? Maybe it is a room for improving balance/matching, so one can add any other resistor as needed after measurement? Nah, it doen't soudn right. There is no mention to that on the datasheet or app. note.

Here is the simulation of both circuits. Vout represents the circuit with the 1ohm resistor, and Vout2 without it:

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Unfortunately I can't see any of your pictures on my computer. So far I could look them up in the documents you refer to, but not this one.

7) I also did not get why they simply did not choose a more straight forward, "less clever" driver, like the one below:

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The results are very close to their choice:

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I don't get why they had the 40.2 resistor in the buffer feedback loop, and the capacitor is differentially set up. I checked on Walt Jung Op Amp Applications Handbook (both chapter 3: Driving ADC inputs and chapter 5: Analog Filters , Douglas Self Small Signal Audio Design, 2nd ed., and Steve Winder Analog and Digital Filter Design 2nd ed., and did not find this construction. This 3.9nF + 40.2 ohms elements on the FB loop are not present on any of the sigma delta drivers I found, ie:

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Souce: http://www.analog.com/media/en/tech...tes/28715432842357460935458165408691AN388.pdf

I have found, however, this exact technique on the OPA1632 datasheet, Fig 14, pg 13. But they do not elaborate any about it.
Glen Bloou also mentions this OPA1632 circuit as an ADC driver on his Handbook for Sound Engineers, but no extra explanation is found.

I'd appreciate if someone could explain it to me, or suggest any further reference.


8) Obviously, the last caps (C1 - C6) act as an usual charge reservoir to the input caps and its roll off just kicks in much later on the freq. response, as expected.

I am also willing to replace those caps for X2Y ones. The reason being that those are important elements concerning balance. And again the X2Y closed matched properties are beyond the realm of the discrete caps.

The filter with output resistor included in the feedback has a very low output impedance at audio frequencies. Hence, the audio-frequency voltage across the ADC's inputs is practically independent of any non-linearities in the input impedance of the ADC. That may be an important advantage when you want to minimize distortion as much as possible.

Without the weird 1 ohm resistors, the output impedance of everything to the left of C1...C3 is an inductance of 2 * 270 ohm * 3.9 nF * R3 in parallel with a resistance of 2 * (270 ohm // R3). With C1...C3 added it is equivalent to an LRC low-pass. By choosing the component values correctly you can get a nice second-order roll-off with whatever Q factor you want to have.

9) what are those "pull down like" 3k3 resistors doing there on the OPA1632 output? They are there on the EVK as well. Could anyone elaborate on that?

An externally hosted image should be here but it was not working when we last tested it.

No idea. Trying to force it into class A? Improve the negative output current a bit?
 
Yes, you are absolutely right! Bad writing of mine... :rolleyes: I should have written "...choosing a 96kHz sampling is that it relaxes the requirements on the digital filter. "

As you said, it will be great to experiment with different digital filters and see the results. If the results are optimal down with fs = 48 kHz, that seems fine for me from the reconstruction perspective, ie, BW up to 20KHz. If a smoother filter will bring any benefit, well then I don't see why not call the trade, as long as the final signal is band-limited to 20kHz.

How sensible does that sound to you?

It sounds very sensible to me to experiment with it. Nonetheless, I'd like to emphasize the relation between hearing pre-ringing and hearing frequency components above 20 kHz.

As a thought experiment, suppose you make an ideal 20 kHz low-pass filter (with no delay, so a non-causal filter). When you insert it into the signal chain, by definition absolutely nothing changes to the frequency components below 20 kHz. When you look at the impulse response in the time domain, you see lots of pre- and post-ringing; in fact the filter with its sin(x)/x-shaped impulse response starts ringing infinitely long before the impulse arrives. If you hear this pre- or post-ringing, you apparently hear the difference between the presence and absence of components above 20 kHz, because that's the only difference there is between the input and output signals of the ideal filter.

Now a bit more practical: the proponents of smooth filtering usually claim that it gives a better sound quality due to reduced pre-ringing. Assuming that the steep filter they compare their smooth filter to is nearly ideal and has a cut-off at 20 kHz or above, this can only be true when they can hear the difference between the presence and absence of the components above 20 kHz.

So there are three possible explanations:
A. The steep filters they compare their smooth filters to are not good enough (for example, have too much passband ripple)
B. They hear things above 20 kHz
C. They are simply wrong with their claim.

Regarding option A, it is interesting to read the bit about pre-echoes and passband ripples in R. Lagadec and T. G. Stockham, "Dispersive models for A-to-D and D-to-A conversion systems", AES preprint 2097, March 1984. They found out the hard way that a linear-phase filter with +/- 0.5 dB ripple was annoying all listeners. In the time domain it had a quite strong pre-echo. You really need quite small ripples to make passband-ripple-related pre-echoes small.

Regarding option B, the only experiment I know of that supports this claim is the 1990's Japanese experiment with gamelan music and electroencephalograms I referred to earlier. Hans van Maanen argued in an article in Linear Audio that all experiments with sine waves are meaningless because the human auditory system is not linear and time invariant.

Regarding option C: there is always the confirmation bias, of course.
 
Not necessarily; I get the impression that CMREFL and CMREFR are decoupling pins for common-mode voltages for internal circuitry. It could very well be that the internal circuitry has maximum headroom when the common mode is halfway the supply rather than halfway the reference voltage.

I see. CMREFx is described as "Analog output", "Internally generated voltage, ties to capacitor" (datasheet, pin description).

The way I understand it, the optimal CM voltage is generated inside the chip, and that is what we get on CMREF pins. (BTW, I can't see any practical use to 2 different L and R references from the user perspective. What application/situation would call for that?) I agree that the CMREFx pins are there probably mainly (exclusively?) for decoupling.

BUFREF is described as "Analog output", "Reference voltage for the buffers driving the analog inputs" (datasheet, pin description). It should be (just a guess here) a buffered version of the CMREFx. But it seems like it is not, because BUFREF and CMREF share almost exact specs: 2.2 kohms output resistance for the CMREF vs 2.4 komhs for the BUFREF; and 10 uA DC current capability for both of them. At first sight that doesn't look like a buffered version of anything...

It raises the question: what is that BUFREF pin doing?

So even if they found later that the chip runs better with the CM voltage a bit higher or lower, the internally generated CM voltage and the pin driving the CM voltage of the op amp driver should be precisely the same. Any scenario I might be missing?

I imagine they did not intend to give us the option of using an alternate external voltage, since they are clear on app note pg 5 "Resistors R1 and R2 trim BUFREF to its optimum value, which must be precisely set to 2.4V".

You probably need details of the internal circuitry to fully understand what is going on here, which you'll never get because of company confidentiality.

Yes, but they should at least explain what will sound better (no put intended, just electrically wise, for now :D). I am just asking to you guys to make sure I am not blundering something here before asking them. My first time with this Arda puppy...
 
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