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Old 4th May 2008, 08:21 AM   #81
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Default JFET Guitar Preamp

Hello Javier and Marito,

Sorry it has taking me so long to post a buffer amp design but I had to think this one through. I decided to post a high-quality, discrete, two-stage buffer amplifier designed specifically as a 9.0V, low-current, on-board guitar preamp. I also decided to do this in two installments: the first on choosing and evaluating a JFET and the second as a description of the complete preamplifier.

I noticed that there are several postings about what JFET to use for the best "tone" and I'm sure everyone has their favorites but I decided to use a J201, N-channel JFET for the first stage of the preamp. This device was chosen mainly because it fit the criteria for the preamp design but also because I happened to have a couple laying about the shop.

I have attached three (3) JPEGs: 1) The first shows an evaluation technique used to determine the Idss and Vgs-off of the J201 (JFET_Evaluation01), 2) the second shows the transfer characteristics of the specific J201 used in the design of the first stage of the preamp (JFET_Transfer01) and, 3) the last JPEG is a schematic of the first stage design of the preamp (JFET_Amp01).

It's a fairly straight forward process to determine the Idss and Vgs-off of a JFET and, if the topology of choice is a self-biased amplifier, it is highly recommended that such a process is applied due to the large variation in JFET characteristics; even within the same part type!

Manually determining the Idss and Vgs-off of every JFET would, of course, be a difficult thing to do in a manufacturing environment but, in the case of a "onesy-twosey" home project, it's not a problem.

I used a 9.0 volt battery as a power source and two 1.5 Volt batteries for the -3.0 V control-voltage. When the Gate and the Source of the JFET are "shorted" together and 9.0 volts is placed across the Drain and the Source you have, in essence, a constant current source; the current measured in this configuration is the Idss. In the case of the J201 I used, the Idss was 510uA.

By placing a negative voltage to the gate of the J201 with 9.0 Volts across the Drain and Source, I varied the negative control potentiometer until I had zero current through the JFET. This negative voltage applied across the Gate and Source was the Vgs-off; in the case of the J201 I used, the Vgs-off was -0.77 Volts.

These are good values for the buffer-preamplifier project because I wanted to design the first stage with a bias current of no more than 100uA and still be high-up enough the transfer cure to be linear with "small" signals.

In order to obtain an Id current of 100uA in the J201 using the self-bias JFET amplifier topology (very similar to the standard triode bias technique), I required a Vgs voltage of -0.38 Volts. To achieve this I placed a 3.9kOhm resistor from the Source terminal of the J201 to ground.

In order to have the Drain of the J201 biased at around mid power supply voltage (4.5V), I placed a 43.0 kOhm resistor from the 9.0V supply to the JFET Drain terminal. In addition, I placed a 1.0M Ohm resistor from the Gate terminal to ground to maintain a "high-impedance" at the input of the amplifier.

With the configuration shown in the Jpeg, I achieved a voltage gain of about 6.8 without the 100uFd by-pass capacitor across the Source resistance. In addition, I was able to achieve a voltage gain of about 23 with the 100uFd bypass capacitor across the Source resistor.

The question you are probably asking yourself is, "why do I need gain in a buffer amp'. The answer will become obvious in the next installment.

In the mean-time, please let me know if you have any questions about what I have posted so-far. I'll answer anything I can before we go on to the final design.

Thank you for your patience, JP Hugsley.
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Old 4th May 2008, 08:21 AM   #82
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JFET Evaluation JPEG

JP Hugsley
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File Type: jpg jfet_evaluation01.jpg (46.1 KB, 1584 views)
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Old 4th May 2008, 08:21 AM   #83
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JFET Transfer Characteristic JPEG

JP Hugsley
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File Type: jpg jfet_transfer01.jpg (34.7 KB, 1492 views)
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Old 5th May 2008, 02:40 AM   #84
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as far as driving capacitive loads goes, the best way to drive into a high capacitance with unity gain buffers made with op amps is to use several (4 is convenient with a quad op amp such as a TL084) in parallel...
http://www.linear.com/pc/downloadDocument.do?id=25632
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Old 6th May 2008, 01:14 AM   #85
xavmdq is offline xavmdq  Argentina
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Hi JP Hugsley!
Because I still have to do an exam, I only post to thank you for explanation. After exam I'll read your post carefully and make you questions.
Thanks!
Marito: I'll also look that design. Thanks.
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Old 13th May 2008, 06:41 AM   #86
xavmdq is offline xavmdq  Argentina
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Default Re: JFET Guitar Preamp

Hi JP Hugley,

Just to add something to your explanation:
If you have different Vp and Idss values, you will need to use the following equations (if you didn't use this equations please correct me):
Vgsq = Vgs for operation point
Vgsoff = Vp = Vgs for Id=0
Idss = Id for Vgs=0
Igss = inverse saturation current (not considered in calculations)
Vp <= Vgsq <= 0V
Rs = -Vgsq / Idq
Vo = Vdd - Id*Rd => if we want Vo=Vdd/2 then
Rd = (Vdd/2) / Id

I have a few questions:
1-
Why do you choose Id = 100uA?
2-
Using FET equation (Vgs related to Id and viceversa):
Id = Idss * (1 - Vgs/Vp)^2 or
Vgs = Vp * (1 - sqrt(Id/Idss))
and with Vp=-0.77V, Id=100uA and Idss=510uA, I get:
Vgs=-0.43V, but you get -0.38V
3-
I calculate the minimum and maximum Vin using:
Vin min = Vp = -0.77V
Vin max = Idss * Rs = 1.989V
DVin = 2.76V
It's enough for piezoelectric pickups? I don't remember but I saw a signal from a piezoelectric pickup and it had a peak voltage of 3V (DVin=6V).
4-
With a gain of 6.8V and taking into account DVin=2.76V we have a variation in the output of DVo=18.77V (DVo must be below Vdd-(Vgsq-Vp)=9V-[-.38V-(-.77V)]=8.61V or 7.61V to have room for battery discharge).
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Old 18th May 2008, 06:32 AM   #87
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Default Guitar Preamp

Hi Javier,

Yes, you are correct; what you have written is the equation quantifying the "square law" relationship between id and vgs. But you must realize that the equation is only an approximation that will agree usually to within 10% of the actual value of id based on Vgs-off, Idss, VDS and vgs. A more accurate equation for the transfer relationship of a JFET exits but it is based on the geometries, doping densities, doping gradients and voltage gradients of the JFET itself. If is much easier to use the "square law" equation but, better still, it is more accurate to determine the transfer relationship of your particular JFET experimentally for use as a "self-biasing" amplifier.

The exponent for the transfer relationship between id and vgs you used was "2" (hence, "square law") however, since the relationship is only an approximation, the exponent can actually vary between 1.5 and 2.5 for a more accurate fit. The "square-law" equation is only an approximation.

There are two reasons why I chose a bias current of 100uA. First of all, it is in a fairly linear region of the transfer curve derived experimentally for the J201 and, secondly, it allows a very low current drain from a nine volt battery (essential for an "on-board" guitar preamp). The gain of the J201 is a little less with a low ID value (proportional to the square-root of ID) but this is not a problem in our application.

Due to the fact that the "on-board" preamp in our discussion is being designed more for an electric guitar with an electo-magnetic pickup (not a piezoelectric pickup), gain is needed in the first stage. The "on-board" preamp is intended, specifically, for a Stratocaster, single-coil, electromagnetic pickup but can be modified for other applications. Of course, if the gain is too much for your application, you can always add a "pad" or attenuator to the first stage. But we can customize this later with real listening tests.

If you are worried about the gain being excessive for transients from the pickup you can "buy" yourself 6.0 dB of "headroom" by using two 9.0V batteries for an 18.0 Volt system but this may not be necessary. You may want to first conduct an A/B comparison test between a 9.0Volt and 18.0 Volt system. "Real World" evaluation and testing is essential in determining what best suits you're application.

Please let me know if this helps. Thanks, JP Hugsley
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Old 27th May 2008, 02:27 AM   #88
xavmdq is offline xavmdq  Argentina
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Hi JP Hugley:

Quote:
There are two reasons why I chose a bias current of 100uA. First of all, it is in a fairly linear region of the transfer curve derived experimentally for the J201 and, secondly, it allows a very low current drain from a nine volt battery (essential for an "on-board" guitar preamp). The gain of the J201 is a little less with a low ID value (proportional to the square-root of ID) but this is not a problem in our application.
Ok. Then the first step is to use a FET with Idss=200uA or more and follow these steps:
- Fix Id (Idq).
- With transfer characteristic obtain Vgsq
- Calculate Rs = -Vgsq / Idq
- DVin = function of Vgsq, Rs, Vp
- Calculate Rd = (Vdd/2) / Id for Vo = Vdd/2
- Voltage gain is: Av ~ 2 * (Idss / Vp) * (Vgsq/Vp 1) * Rd

Is this correct?

Quote:
Due to the fact that the "on-board" preamp in our discussion is being designed more for an electric guitar with an electo-magnetic pickup (not a piezoelectric pickup), gain is needed in the first stage.
But, I have a piezoelectric pickup (PP) (the guitar actually have electromagnetic pickup, EP, but I added PP and thats why I need a buffer to mix the two signals). I don't touch the original circuit (EP, 9V battery, vol + tone controls): my idea is to mix both signals using this buffer. In both, I have the same signal level (2-3V peak).

Please, continue with the following part. Thanks.
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Old 4th June 2008, 05:14 AM   #89
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Default JFET Preamp

Hi Javier,

I've been off-line for a week and I am just now getting back to DIY.

The calculations that you have written and your line-of-reasoning are correct. However, please understand that there are many JFET's available all with different characteristics. You must choose the one that you feel is best for your application. In my case, my primary concern is for "battery life"; for that reason, I decided on the J201 which can be biased between 50uA and 250uA depending on it's particular transfer characteristics. There are other JFETs that are optimized for noise and/or linearity but they may have much higher Idss and Vgs-off (pinch-off) values and, depending on the bias point, may drain a 9 Volt batter in less than 100 hours. With an overall current draw specification of 250uA for the entire on-board circuit, a nine volt battery can last over 2,000 hours.

For example, if you have a JFET with an Idss value of 3mA and a Vgs-off of -6.0 Volts, you may want to self-bias a common source amplifier with a Iq of 1mA. If you have two such amplifiers on your on-board circuit, that would be a total quiescent current draw of 2mA which would translate to a 9.0 Volt battery life of about 250 hours.

In any case, you would most likely bias your amplifier at about 1/3 the Idss value for best linerity (only a rule-of-thumb). For best results, you could, with a simple voltage source and current meter, determine the transfer characteristics of your particular JFET and, using Excel, graphically illustrate the transfer curve of any JFET you like (the accuracy would depend on the number of data points and the sophistication of your curve-fitting software).

The most striking realization you would have from such an excercise is discovering the large variation in JFET characteristics even among JFETs of the same part type.

Would you be interested in doing such an excercise? Would you like for me to send you some graphic samples of such an excercise?

Please let me know.

BTW: I have never designed a preamp for a piezoelectric pickup. It would help to know the source impeadance of such a pickup. Do you have this information? If not, could you give me the name and model of your guitar, maybe I could reseach this information myself.

Thanks, JP Hugsley.
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Old 12th June 2008, 05:47 PM   #90
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Hi guys,
First, I'm nowhere near you in the theory department but I have been building electronics for years and know a bit about it - enough to get me by.
But I'm having a problem biasing the Drain on this FET preamp circuit - not the one shown above, but Donald Tillman's:

http://www.till.com/articles/GuitarPreamp/

He recommends trying a few JFETs to get one with which the Drain bias will be 5 - 7 volts. I tried 10 of them and said bias is always 8.4 to 8.66 volts.
This bias is measured Drain to Ground, right?

I found this article:

http://www.diyguitarist.com/Guitars/...itarPreamp.htm

in which a trim pot is use for the 2.2k source resistor to make biasing easier. When I tried it the drain bias could indeed be set to around 6 volts and the circuit does work . . . Way TOO well. The amplification is far more than the 3.5 db described in the original article. I've seen the circuit used by lots of people successfully and I can't figure out why mine doesn't work. I've checked everything, even building two of them just to make sure I got it right.
I'm curious about how all the FETs I tried come out so similar and yet out of range.

Any ideas on why or how I can get this little beast in line?

I suppose I should just start over using the circuit shown above, but I don't like getting beat by such a simple device that everyone else seems to have no problem with.

Any info or pointers would be much appreciated.
Thanks,
Ken
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