Critique my PCB! Headphone amplifier

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Right, as this is my first first PCB, my first time using Eagle and my first (production) headphone amplifier...

...your brutal honesty and constructive feedback will be welcome :)

Notes:

  • The schematic shows only the left channel (the right is identical)
  • The design uses one dual opamp for the amplification stage (OPA2227 or 1611), and a single BUF634 buffer for each channel.
  • There are three IC decoupling capacitors for each power rail - an electrolytic 100uF and two X7R SMD caps (2.2uF and 22uF). The X7Rs are placed directly under the DIP8 sockets of each IC to get nice and close to the pins.
  • The PCB - red is the top layer, blue on the bottom
  • The entire bottom layer is a ground plane, split into seperate signal ground (SGND) and power ground (GND) planes. These will merge off-board, at the power supply.
  • Most traces are 0.7mm in width, while the power traces are 1.5mm.

Apart from a general critique / trouble spotting, I've got a couple of questions:

  1. I understand the output resistors - R3 and R5 - need to dissipate a fair amount of power. Would 1/2W resistors be sufficient for this application?
  2. In an attempt to keep the ground planes unbroken, I resisted the temptation to create vias, which meant some of the traces are slightly longer than I would have liked - particularly the V+ and V- traces right at the bottom of the board. Will this present an issue? All signal traces were given priority (as short as possible).

Again, any feedback welcome.

Thanks!
 

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Let's start from the schematic first.

1. You do not need R3 at all. If you examine the reference headphone amplifier schematic in LME49600 datasheet (same IC as BUF634 inside) and similar reference schematic in the BUF634 datasheet you will notice that R3 is not there. And there is no big current flowing between the op-amp output and the buffer input to worry about.
2. RF filter at the input does not require such a huge physical size capacitor. I am sure there much smaller size parts for this.
3. I would recommend using just one ceramic decoupling capacitor instead of two per rail per IC. Also in your mostly through-hole design SMD parts look out of place. You can get small size leaded ceramic capacitors instead.

PCB:
1. Your GND plane has so many cuts and so many traces crossing those cuts that it makes the entire idea of having the GND plane useless. I recommend following the current flow along the traces to get an idea of how return current would flow. This will give you better idea how to lay out the GND plane.
2. There is no electrical connection between the power GND and signal GND which should be there for correct functioning of the amplifier.
3. When you route the supply traces keep in mind that they first go through the decoupling capacitors from big to small and only then hit the IC's pins. In your layout the supply traces first go to the IC pins and then continue to the decoupling capacitors.
4. Your schematic allows for nearly symmetric layout, which makes routing power traces more convenient along the middle of the PCB while left and right channel's signal can go along either side of the PCB. Note that the inputs are usually separate due to the use of RCA sockets, so you can use two separate input connectors and one common ground output connector.

Good luck with your project and don't give up! We all do mistakes at the beginning and have to learn to perfect our skilles.

Regards,
Oleg
 
Hey Abza, I agree with Oleg that the 680pF input cap can be a much smaller type, for example a surface mount C0G multilayer ceramic capacitor.

Also, if you're comfortable using SMT parts for the decoupling caps, why not do the same for the other components? That will reduce the PCB size, making it cheaper to produce and easier to fit in whatever case suits your fancy. For example, R3, R5 and the gain and feedback resistors can be replaced with high-quality thin-film (not thick-film!) SMD types. For example, the Susumu (RG series) and Panasonic thin film resistors in an SMD 1206 package are good parts and much smaller.

If you want to drive sensitive headphones or in-ears, you might want to go with a smaller isolation resistor at the output; for example, see this article. Edit: smaller values will also reduce their need to dissipate power.

I would also drop the 100μF electrolytic capacitors for the OPA2227; it won't be loaded heavily. You could use a small resistor (like 100Ω for the OPA2227, 10Ω for the BUF634) to create a low-pass filter with the decoupling capacitors. See this article from Bruce Carter, p.47, second paragraph.

Finally, put your feedback resistors as close as possible to the high-impedance inverting input pins. This helps to reduce noise, EMC pickup other nastiness.
 
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@OlegSh, @Idiosyncrasy - thanks so much! All extremely valuable feedback.

@OlegSh: Your GND plane has so many cuts and so many traces crossing those cuts that it makes the entire idea of having the GND plane useless. I recommend following the current flow along the traces to get an idea of how return current would flow. This will give you better idea how to lay out the GND plane.

Right, clearly I need to do a little more reading about how to lay traces over ground planes. Any suggestions as to example PCBs that do this well, or a tutorial that covers this?
 
Next bash! Changes as per the above:

  1. Removed the resistor between the opamp and the buffer (previously R3)
  2. Removed the 2.2uF decoupling capacitors (the 22uF ones remain under each IC).
  3. Removed the 100uF decoupling caps for the OPA2227
  4. Ensured the power rails run mostly through the centre, and massively reduced the number of times traces intersect the ground planes
  5. Power now runs through the caps before entering the ICs
  6. Feedback resistors moved close to the -IN terminals of the opamp

Things that have stayed the same:

  1. I've kept the SMD IC decoupling capacitors, the enormous 680pF input capacitor and my resistor choices... purely because I have them already :) I also don't mind a mix of SMD/through hole components.
  2. I still haven't connected the ground planes - again, these will be merged by cable on the power supply side.

Let me know if I'm heading in the right direction - particularly when it comes to the new layout of the ground planes. But all suggestions welcome!
 

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This one is not much better. The reason is that power traces do not have GND plane underneath them and you still have traces crossing the cuts in the GND plane. I think moving power entry connector to the space between two BUF634 and reducing to only two electrolytic caps (one per rail) can simplify the routing of power supply network and separate it entirely from the signal network. Just make both channel's signals flow around the BUF634's. Then make one continuous GND plane under the entire board, no cuts.

Regards,
Oleg
 
Thank you so much, fellas!

OlegSh: The reason is that power traces do not have GND plane underneath them...

^ Aha, okay! So basic noob question: why is it beneficial to have the power traces run directly above the GND plane?

OlegSh: Then make one continuous GND plane under the entire board, no cuts.

^ So if I flood the entire bottom with a single GND plane, would I just dump the idea of a separate signal ground and just use the GND plane for everything instead? Or keep the signal ground traces separate by routing them on top?

Mark Whitney: ...don't mix the currents in the ground plane...

^ Hi Mark! Could you elaborate on this a little please, or send me a link where I can find out more?

abraxalito: ...separation of the supplies to the opamp and output buffer through filtering...

^Hi abraxalito! Unfortunately the schematic/PCB images in that thread are no longer working. Do you have any other information regarding the filtering and separation of the supply?

Thanks all
 
From reading the posts again I notice that the OP went for some polymer caps (560uF). I reckon those aren't the best bang for the buck now as Nichicon HZ caps offer similarly low ESRs but for cheaper. So my suggestion is to decouple your opamp with 1000uF/16V Nichicon HZ and feed those caps from the BUF634 rails via SLF7045-102 (1mH TDK inductors).
 
The current loops to the capacitors from the PSU and the current loop returning from the output are passing through the same part of the ground plane. Post 7 left channel shows some of the power loops and the right channel the output loop. By moving the power connection and capacitors to one side of the IC and the output to the other you remove the output voltage error caused by the power current.

The ground plane on the output side of the IC is a good place to connect the SGND to the (power/output)GND.

Fixed the SGND error in the schematic.
 

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Woah ho ho, thanks @JPS64! I'll take a look a little later this evening, but first glance looks awesome.

A lot to be learned here. I can immediately see what @OlegSh was referring to when insisting that the traces try not intersect the ground cuts - you've made it look easy :)

Can anyone recommend a good tutorial/place to learn about how to become comfortable following current paths, detecting loops etc? Must admit I have a hard time visualising this, where others seem to spot these issues immediately.
 
Yeah, the layout by JPS64 is really great and gives very informative visual impression!

As for the return paths and such, the rule is very simple, if there is a trace where current flows "forward" then there should be a closely coupled trace where the current can flow "backward". If the return trace takes a detour (or GND plane under the "forward" trace has a slot forcing the return current to deviate from its ideal path) this will immediately increase the loop area created by the "forward" and "backward" current paths and introduce extra parasitic inductance. If such loop is connected to the high impedance node it can act as aerial picking up all kinds of noise from the surrounding. It can also radiate noise if high (supply or output) "pulsing" currents flow along this loop and induce noise into other sensitive circuits around. If excessive loop area is present around sensitive nodes it can severely degrade circuit performance and sometimes impair stability, for example when decoupling capacitors are placed too far from the supply pins of high speed op-amp. For more info have a look at this tutorial. It deals with mixed analog/digital designs but has some useful info with figures. There are many other tutorias, just google for "PCB layout" in combination with "grounding".

Regards,
Oleg
 
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Right, next version!

Changes:

  1. Pretty much everything - components remain the same (as I have them in my parts bin) but layout is much more clearly defined between signal and power sections
  2. No intersection of power traces, power traces remain above the GND plane
  3. Signal traces remain over the signal ground as far as possible
  4. As @Mark Whitney suggested, SGND and GND connect on the schematic
  5. As @OlegSh suggested, SGND and GND connect right at the output and power terminals (a thin ground path connecting them)
  6. Lots learned from @JPS64's layout, particularly with regards to using a small trace within the GND plane for sections where routing top traces would be impossible. I managed to get away with just one (top left 100uF capacitor)
  7. Power rails now each originate from the terminal, rather than daisy-chaining or branching off.

I know there is a lot of dead space to be removed - the layout can be significantly tightened up - but is this an improvement with regards to the trace and ground layout?

Thanks everyone!
 

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It's getting better, however your feedback lines are unnecessarily long.

R1l and R1R should go to the middle of the pcb, under and above the output resistors; that would allow you to shorten tracks significantly.

Ideally, the R0 resistors should also go to the middle, in order to sense the output ground. Speaking of the output gnd, there is no reason to link it to power ground through a thin track. Actually the thicker the better there. Just make the two groundplanes overlap at the right end of the sgnd groundplane

I don't get why your 680p CIN2 capacitors are that big compared to the much bigger CIN1 caps ?

I see you plan on using 22uF x7r caps. Beware that x7r caps usually have strongly reduced capacitance vs DC voltage bias. A typical 22uF/25V murata 1210 X7R cap will only have 7.3uF at 15VDC. That's actually less than a 10uF/50V cap from the same serie at 15Vdc. Murata (and other manufacturers) have simulation tools on their website to help you determine what you actually get.
 
I'm with Ben.

Keep in mind that the feedback network should be very tight and RG0 should be connected closer to the output since you want the feedback to correct the error at the output not the input. The RG1 should also go between the op-amp and the buffers to minimize the feedback loop area. Take your time. Analyze what you see and try again. Also make those huge RF filter caps at the inputs small in size since these huge caps have such a high parasitic inductance that they will not work effectively as RF filters. Also turn the buffers by 90 degree as JP did in post #12, it will help you routing the power supply and signal traces more conveniently. If you'll do everything right you will not have to introduce many GND plane cuts to prevent mixing signal and supply return paths.

Regards,
Oleg
 
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