Please review my first headphone amp design

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The input stage was inspired by Cavalli's SOHA-II, but I have choose different design for output. I use source follower loaded to Norton level shifter fed by op amp DC servo (inspired by TI's LME49600 reference design) via current mirror to drive simple MOSFET source follower with SSC. So I have a fully DC coupled amplifier. What do you think? I'm doing first steps in analog electronics.

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Some thoughts:

1. The stage 2 current source is a current mirror, meaning IC1A would have to deliver a nominal 20 mA. Bit high for my tastes. Adjust R10 up and R9 down for about a 1:4 ratio; also 20 mA is a bit beyond the sweetspot of a BC547, a BC337 or similar for Q6 may be the better bet here.

2. Stage 2 output impedance (= ~R8) is a bit on the high side. Hint: nonlinear input capacitance of Q9. I'd split R8 between maybe 2k and 200R, with about a 22-47 µF (63-100 V) electrolytic in parallel to the 2k. The output tap goes between the resistors, or alternatively (preferred) move the 200R into the stage 2 - stage 3 connection, physically placed directly at Q9 gate so it makes a nice gate stopper.

3. The amount of negative feedback provided is very low. 6922 mu is like 30-ish, and you're shooting for an ideal closed-loop gain of like 16-ish. That can't be more than 6-10 dB of excess loop gain. Such low amounts may be sonically detrimental rather than beneficial. The breaking even point is at about 20 dB, and ideally you want 40+ dB.

4. And speaking of closed-loop gain, you typically do not need 20+ dB in a headphone amplifier, 10-14 dB tends to be plenty. Those tubes will be noisy enough as-is!
 
Is the phase of the input stage correct?
The input is connect to the -IN and the feedback is connected to the +IN of the LTP.

I agree on the closed loop gain.
Headphones are so sensitive that the amps often do not need any gain, even when replay levels are very loud.
 
Is the phase of the input stage correct?
The input is connect to the -IN and the feedback is connected to the +IN of the LTP.
Good catch. The normal feedback arrangement will obviously not work if there is no inverting amplifier stage in the loop, or rather you'll get positive feedback and a fine oscillator instead.

Some minor reshuffling of stage 1 should fix that, but overall phase is inevitably going to be inverting.
 
Some thoughts:

1. The stage 2 current source is a current mirror, meaning IC1A would have to deliver a nominal 20 mA. Bit high for my tastes. Adjust R10 up and R9 down for about a 1:4 ratio; also 20 mA is a bit beyond the sweetspot of a BC547, a BC337 or similar for Q6 may be the better bet here.

2. Stage 2 output impedance (= ~R8) is a bit on the high side. Hint: nonlinear input capacitance of Q9. I'd split R8 between maybe 2k and 200R, with about a 22-47 µF (63-100 V) electrolytic in parallel to the 2k. The output tap goes between the resistors, or alternatively (preferred) move the 200R into the stage 2 - stage 3 connection, physically placed directly at Q9 gate so it makes a nice gate stopper.

3. The amount of negative feedback provided is very low. 6922 mu is like 30-ish, and you're shooting for an ideal closed-loop gain of like 16-ish. That can't be more than 6-10 dB of excess loop gain. Such low amounts may be sonically detrimental rather than beneficial. The breaking even point is at about 20 dB, and ideally you want 40+ dB.

4. And speaking of closed-loop gain, you typically do not need 20+ dB in a headphone amplifier, 10-14 dB tends to be plenty. Those tubes will be noisy enough as-is!

The main purpose of stage 2 is to provide variable voltage drop across R8 controlled by DC servo. More current = more drop. I need to drop about 40V there. So with less current even more resistance required. 20mA is the value that can be safely provided by almost any general purpose op amp.
 
Good catch. The normal feedback arrangement will obviously not work if there is no inverting amplifier stage in the loop, or rather you'll get positive feedback and a fine oscillator instead.

Some minor reshuffling of stage 1 should fix that, but overall phase is inevitably going to be inverting.

Feedback is connected to inverting input of differential pair. Inverting input is always on the same side as output point (like in CC).
 
Some thoughts:
2. Stage 2 output impedance (= ~R8) is a bit on the high side. Hint: nonlinear input capacitance of Q9. I'd split R8 between maybe 2k and 200R, with about a 22-47 µF (63-100 V) electrolytic in parallel to the 2k. The output tap goes between the resistors, or alternatively (preferred) move the 200R into the stage 2 - stage 3 connection, physically placed directly at Q9 gate so it makes a nice gate stopper.

Anyway I didn't quite understand your advise with capacitor. Can you explain? Thank you.
 
Anyway I didn't quite understand your advise with capacitor. Can you explain? Thank you.
If you split the 2k2 resistor into a 2k and a 200R part and then put a suitable large capacitor in parallel to the 2k part, the result still looks like a 2k2 resistor at DC. At AC, however, the capacitor eventually shorts out the 2k part, leaving only the 200R. So you get the same DC voltage shift as before, but output impedance of this stage has reduced by more than an order of magnitude.

Adding a buffer as you've done now is another option, of course.
 
If you split the 2k2 resistor into a 2k and a 200R part and then put a suitable large capacitor in parallel to the 2k part, the result still looks like a 2k2 resistor at DC. At AC, however, the capacitor eventually shorts out the 2k part, leaving only the 200R. So you get the same DC voltage shift as before, but output impedance of this stage has reduced by more than an order of magnitude.

Adding a buffer as you've done now is another option, of course.

Wow it works great! It reduces THD two times. Thank you for advise!
PS: In this case RC time constant will be 200*C, right?
 
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There's actually two of 'em, but that's the one you are going to be interested in, yes.

I've done some simulation and got very strange result. The lowest simulated THD (I tried 1kHz and 10kHz) i've got was with very small capacitance, about 80nF and without gate resistor at all. But even large capacitances are better than no cap. Can you explain it? I'm confused.
 
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