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Old 1st February 2015, 01:44 AM   #1
rjm is offline rjm  Japan
Richard Murdey
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Default Another take on the Diamond Buffer

I'll throw this out here as I imagine not everyone reads the blogs.

I haven't given too much thought to the transistors yet, the selection in LTSpice is anyway so poor that I just leave generic placeholders BC327/337 in there and hit "run".

The main idea, apart from the oft-implemented current sources, is the RC filters in front of the output transistors. My other interest is fine-tuning the ratio of driver to output bias for best performance.
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File Type: png Sapphire3 dev00.png (37.1 KB, 581 views)
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Old 3rd February 2015, 01:43 PM   #2
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What a pity that I had not read the blogs!

I should have read it before I started my headphone amp project.

Thank you RJM.
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Old 5th February 2015, 07:11 AM   #3
arpagon is offline arpagon  Bulgaria
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And what is the purpose of such schematic's "castration" with these RC filters?
According to sims, they rolled-off the frequency responce to ~ 300kHz at -3 dB.
If you want LPF, put it in the front of the buffer.
What about the output transistors' biasing - read carefully Walt Jung's article for diamond buffers.
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Old 6th February 2015, 11:17 AM   #4
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Consider it an experiment - to see if it made any difference. In principle it should not affect the audio bandwidth present or not. In practice, it did ... so it is at least worth looking into.

The position after the driver pair vs. at the input has the advantage of improving PSRR slightly at high frequencies, and the disadvantage of increasing the output impedance slightly. Neither should have a substantial influence on the output characteristics though.

The output bias current is 30 mA. I tried several settings, this is in the region I prefer. It can be increases if more class A power into low impedance loads is desired, though crossover distortion may increase if you do.

A more recent version of the schematic is attached. I propose to drop the RC filter - still under evaluation but overall I think dampens the sound a bit too much.

Walk Jung on Diamond Buffers, for reference.
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File Type: png sapphire buffer 3 02.png (71.6 KB, 455 views)
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File Type: zip Sapphire3 buffer trial 02.zip (1.3 KB, 9 views)
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Last edited by rjm; 6th February 2015 at 11:26 AM.
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Old 7th February 2015, 04:06 PM   #5
arpagon is offline arpagon  Bulgaria
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If we speak about PSRR and CCS used, I will propose you a (slightly) different approach.
Simulated PSRR with two CCS (as in your schematic) is ~ -71 dB. (see fig.1)
If you use current mirrors with JFET CCS (fig.2), the simulated PSRR is the same (see fig.3).
So I personally prefer the latter approach since the fine tuning of output transistors' quiescent currents is easier (at the expense of one more transistor) - I mean that varying with only one resistor's value you change simultaneously the currents via both driver transistors. And you can even put a trimpot instead of fixed value resistor.
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File Type: png PSRR-1.png (75.5 KB, 384 views)
File Type: png PSRR-2.png (141.9 KB, 369 views)
File Type: png PSRR-2a.png (90.5 KB, 343 views)
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Old 7th February 2015, 05:31 PM   #6
ammel68 is offline ammel68  United States
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Hi arpagon,

I would like to build the circuit you posted above, but I have a few questions:

1) Do you know if the circuit would be stable as drawn?

2) Is power supply voltage +- 25VDC?

3) 2SK117 is difficult to find. There are some on eBay from Asian sellers, but most look fake judging from their photos. One seller has some GR grade 117s that appear authentic, but who knows?
Is there a different JFET that'll work and is easier to find?

4) Where would the trimmer pot go in the circuit and what resistor(s) would you measure the voltage across in order to set the bias?

5) Is there a way to control DC offset, or will it be low enough not to worry about?

Thank you!
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Old 7th February 2015, 09:59 PM   #7
arpagon is offline arpagon  Bulgaria
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Hi ammel68,
I do not want to hijack the rjm's thread (may be the dedicated topic about Diamond Buffers should be opened) but I'll answer you anyway.

1. About stability - I always use such schematic inside of the NFB loop. If you plan to use the buffer without the NFB loop, you must put C3 into the game (see fig.1). The simulated response of square wave signal is given in the fig.2.
2. The PSU can be +/- 25V without the problem if you stay in the SOA of the output transistors and if your input signal amplitude is below 15V (for given transistors - BC550/560).
3. Instead of 2SK117 you can use 2SK264, BF245 and almost all N-JFET transistor which is low-noise enough. According to Walt Jung the JFETs with long base is preferable (with higher U pinch-off voltages).
4. For the trimpot look at the schematic in the fig.3
5. The offset of schematic is small enough even to use it without decoupling caps (if you match transistors).
And finally - if you want to go into high input voltages, consider use of C1 - it's connected with dissipation of minority carriers from the base (see fig. 4 without it)
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Old 8th February 2015, 02:22 AM   #8
ammel68 is offline ammel68  United States
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Hi arpagon,

Sorry, I wasn't trying to hijack Richard's thread, either.

I'm looking a great sounding discrete buffer to use without incorporating it into a NFB loop and be able to hang a volume pot in front of it for signal level control.

There are already several designs floating around that use a op-amp for the input stage along with a diamond buffer for the output stage...been there and done that already.

Since your buffer uses BC550/560 BJTs, that rules out the use of a volume pot in front of it.
Guess I was "putting the cart before the horse" so to speak.
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Old 8th February 2015, 05:25 AM   #9
arpagon is offline arpagon  Bulgaria
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Sorry I forgot the pictures in the previous post
I'm attaching them here
Attached Images
File Type: png PSRR-3a.png (142.0 KB, 72 views)
File Type: png PSRR-3b.png (73.7 KB, 68 views)
File Type: png PSRR-5.png (147.0 KB, 79 views)
File Type: png PSRR-6.png (65.5 KB, 76 views)
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Old 8th February 2015, 09:10 AM   #10
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Richard Murdey
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@ammel68

You don't really need to worry about stability with these circuits, there is neither feedback nor gain so they do what they do regardless. All you are looking at is, ultimately, how it sounds, or as these things tend to devolve, how it looks in LTSpice.

If you want a buffer with a volume control on the front, you can use BJTs if its for line level use (I've done exactly that.). For headphones the impedance may be too low and you'd need to rethink things (should be fine with a 10k pot though...). JFETs are the obvious answer but may not be ideal directly driving the output transistors. You might want to add a stage.

@arpagon

I've seen that version (more or less) before... here, though maybe other places too. I haven't quite worked out the advantage of what advantage current mirrors like that have over the traditional CCS config I show above, though I understand that the JFET allows the bias current to be adjusted/trimmed which is of course useful, and come to think of it its perhaps best to set the current in common for both phases.

I notice in the schematics you've added a couple more capacitors, C1 and C3. I'd appreciate it if you could explain your reasoning for the position and values.
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Last edited by rjm; 8th February 2015 at 09:12 AM.
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