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Old 24th January 2015, 06:32 AM   #1
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Default Another implementation of Class A buffer for headphone

Hi all:

My colleague praises highly the PPA1 ( The PPA Project )
He wonders whether I can implement a similar design.

I took the challenge ( I am no EE) and made something.

Here are some consideration or criteria for my implementation:

1. low noise
2. capable to drive high impedance cans like Beyer 600 ohm models and
low impedance AKG 702
3. Class A
4. DC-coupled

I am a newie in PCB layout. Comments are welcome.
Attached Images
File Type: png UGHPA-schematic.png (51.7 KB, 519 views)
File Type: png UGHPA-layout-without-GND-planes.png (39.4 KB, 500 views)
File Type: png UGHPA-layout-with-GND-planes.png (46.9 KB, 466 views)
File Type: png UGHPA-layout-top.png (39.5 KB, 451 views)
File Type: png UGHPA-layout-bottom.png (38.3 KB, 442 views)
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Old 24th January 2015, 06:35 AM   #2
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Other modifications made:

1. no gain - a DAC with 2V output is load enough
2. pot is put behind opamp - simulation suggests that it has lower noise when volume is less than 50%
3. no global feedback, only locally feedback to opamp
4. remove virtual ground, as I will supply it with dual power +12/0/-12
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Old 24th January 2015, 06:40 AM   #3
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Here is the Tina file for doing the simulation.
Attached Files
File Type: zip PPA-Buffered-cap.zip (6.4 KB, 41 views)
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Old 24th January 2015, 10:37 PM   #4
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This is like a cross between a PPA, a Lehmann clone and an O2.

I doubt it'll perform as well as the original PPA design, especially in terms of distortion. That one used a Jung multiloop topology, while you've got an open-loop buffer there. Bit of a waste of an ADA4627 IMO, I wouldn't expect that one to be the bottleneck (in the circuit as shown, a '5532 would be plenty). Should still be quite decent overall though, as long as you give the buffer a healthy amount of standing current. Not sure what the buffer will think of up to 2.5k of source impedance though.
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Old 25th January 2015, 05:34 AM   #5
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Quote:
Originally Posted by sgrossklass View Post
This is like a cross between a PPA, a Lehmann clone and an O2.

I doubt it'll perform as well as the original PPA design, especially in terms of distortion. That one used a Jung multiloop topology, while you've got an open-loop buffer there. Bit of a waste of an ADA4627 IMO, I wouldn't expect that one to be the bottleneck (in the circuit as shown, a '5532 would be plenty). Should still be quite decent overall though, as long as you give the buffer a healthy amount of standing current. Not sure what the buffer will think of up to 2.5k of source impedance though.
Thank you sgrossklass!

As I mentioned in the posts above. I employ a different feedback topology to that of PPA's. Yet, I am unable to tell the pros or cons or each design. An engineer tells me that local feedback addresses HF issue whereas global feedback addresses LF issue. I need to study the Jung multiloop again and see if I can tell what's the difference it makes.

Choice of opamp:

I run simulation with OPA1611 and OPA827, simply because TINA has library of these opamps. But EAGLE only provides footprints of ADA4627 that I use it in the PCB layout.

When I use OPA827 for the simulation, I get 3mV offset voltage at the output. I guess that I will get similar result if OPA211 is used.

In terms of numbers, aka specs, 5532 is good enough, I agree. But sound wise, I do not like the sound of 5532 produced from other headphone amps. Not sure whether 5532 will work fine in this design or not.

Source impedance for the buffer:

Yeap, thank you for pointing it out. I had not considered this issue.
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Old 25th January 2015, 08:21 PM   #6
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Quote:
Originally Posted by B&W_arthur View Post
As I mentioned in the posts above. I employ a different feedback topology to that of PPA's. Yet, I am unable to tell the pros or cons or each design. An engineer tells me that local feedback addresses HF issue whereas global feedback addresses LF issue. I need to study the Jung multiloop again and see if I can tell what's the difference it makes.
Since the output buffer tends to be a major source of distortion (I would expect 0.0x% or even more under heavy loading, dominant 3rd), it's always better to have it inside the feedback loop. This is much harder to get stable though. Now the Jung multiloop topology makes the opamp stage slow due to high noise gain, much slower than the buffer, in which case stability is easily achieved again.
Quote:
Originally Posted by B&W_arthur View Post
In terms of numbers, aka specs, 5532 is good enough, I agree. But sound wise, I do not like the sound of 5532 produced from other headphone amps. Not sure whether 5532 will work fine in this design or not.
It is likely to be rather bored by its job. Samuel Groner measured some bog standard TI NE5532s (the cheapest 5532 variation you can buy), and 20 kHz THD in a unity-gain buffer at 7.75 Vrms (+20 dBu) measured no higher than 0.004%, limited by common-mode distortion. It easily drives 10 kOhms anyway, and at the low surrounding impedances neither input impedance distortion nor offset generated by bias currents (500 nA typ in the TI part) is going to be a problem. Rail decoupling seems fine, too.

Extrapolated to 2 Vrms, I would expect 20 kHz THD of maybe 0.001%, i.e. -100 dB. Even the most conservative estimates would consider this level inaudible.

I would consider adding some input filtering though, in order to keep RF out, maybe one 100 pF to ground or better case directly at the input and another to ground after the 100 ohm series resistor.

I can't really wrap my head around your PCB layout - the details are too fuzzy to work out which layer is for what. If you use a ground plane, make sure there are no "islands" in it, no big ones anyway.

Last edited by sgrossklass; 25th January 2015 at 08:24 PM.
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Old 25th January 2015, 09:15 PM   #7
agdr is offline agdr  United States
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Quote:
Originally Posted by B&W_arthur View Post
When I use OPA827 for the simulation, I get 3mV offset voltage at the output.
This will go away (typically less than 150 microvolts, = 0.150 millivolts) when you fix this:

Quote:
Originally Posted by B&W_arthur View Post
Other modifications made:
3. no global feedback, only locally feedback to opamp
Like sgrossklass says, consider a multiloop design. I regularly get around 20uV - 50uV DC output offset with an OPA827 wrapped around a LME49600 buffer chip with my O2 booster board project. That is due to the feedback loop around both chips.

Last edited by agdr; 25th January 2015 at 09:22 PM.
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Old 27th January 2015, 07:52 AM   #8
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20-50 V is quite impressive, especially for a FET input part - looks like Vos often is a fair bit smaller than the specified .15 mV maximum. A number of BJTs would be envious.

It's not like 3 mV would be much to worry about or anything. Even in a fairly sensitive in-ear of 125 dB SPL / 1 V sensitivity, this would equal the max excursion at about 70 dB SPL, which should not be taxing most anything. I would be more worried about the rather finite PSRR of the buffer... fairly clean supplies may be needed like that.
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Old 27th January 2015, 11:59 AM   #9
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Quote:
Originally Posted by sgrossklass View Post
20-50 V is quite impressive, especially for a FET input part - looks like Vos often is a fair bit smaller than the specified .15 mV maximum. A number of BJTs would be envious.

It's not like 3 mV would be much to worry about or anything. Even in a fairly sensitive in-ear of 125 dB SPL / 1 V sensitivity, this would equal the max excursion at about 70 dB SPL, which should not be taxing most anything. I would be more worried about the rather finite PSRR of the buffer... fairly clean supplies may be needed like that.
Yeap. I did taken the PSRR into consideration.
I am going to try the Jung/Diddden regulator to supply current to the buffer.

Regarding the idea of multi-loop feedback.
I did a simple simulation with TINA.
Out of my surprise, the noise does not rise after the insertion several
feedback resistors. I cannot get a copy of the original jung article...

Regarding your comment about PCB layout, I am studying...

http://www.ti.com/lit/ml/slyp173/slyp173.pdf

Analog Devices : Analog Dialogue : PCB Layout

Hope, I can have a clear idea about the layout...
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Old 27th January 2015, 12:00 PM   #10
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Quote:
Originally Posted by agdr View Post
This will go away (typically less than 150 microvolts, = 0.150 millivolts) when you fix this:



Like sgrossklass says, consider a multiloop design. I regularly get around 20uV - 50uV DC output offset with an OPA827 wrapped around a LME49600 buffer chip with my O2 booster board project. That is due to the feedback loop around both chips.
Thank you for your encouragement~
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