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Old 7th May 2014, 09:43 AM   #1
00940 is offline 00940  Belgium
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Default Optimizing a TPA6120a2 layout

Hello,

I'm trying to draw a small board for the TPA6120. The idea is to have a kind of all-purpose headphones buffer. This means:
- jfet input to interface easily with a volume control at the input if needed;
- it has to stay small (5*5cm)
- no onboard PS nor potentiometer, just a bare gain stage.

Here are the schematic/current layout:

Click the image to open in full size.

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Click the image to open in full size.

A few questions to the more knowledgeable around here:

- would those inductors be suitable at the output ?
- the output tracks in between the output pins and the output inductors inputs is quite long and under a groundplane. The datasheet points out that a capacitive loading can lead to instability. Should I remove the groundplane over those tracks ?
- same kind of question about the tpa6120 feedback resistors... the way they are now, they completely free the sides of the TP6120 for PS bypassing. But it makes the feedback a bit longer than necessary. Too long ?
- should I decouple the input opamps PS with a small LC or RC filter ? I could fit some ferrites and 100uF caps above the two single opamps I think.

Thanks for any comments
Attached Images
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File Type: gif tpaboard.GIF (58.2 KB, 252 views)
File Type: gif tpaboard2.GIF (36.1 KB, 134 views)
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Old 7th May 2014, 12:09 PM   #2
marce is offline marce  United Kingdom
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A trace over a ground plane on a 1.6mm PCB aint going to have that much capacitance, 0.44pF/cm approx. so basically you can ignore it.
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Old 7th May 2014, 02:57 PM   #3
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I would loose the thermal relief, change the one large via under the TPA to several small
tented vias and bake it in a toaster oven.
Tenting the vias under the TPA will leave the top side free of LPI but the bottom
will be covered. This has the benefit of less wicking of the solder into the vias under
the chip.
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Old 7th May 2014, 08:11 PM   #4
00940 is offline 00940  Belgium
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@marce: thanks, that's one worry I can scrap from the list.

@Avro Arrow: I hear you but... I only need very few boards (I'll get three from Oshpark I think). I know I can solder them by hand ad I'm a bit reluctant to switch methods for just this project. It could be a nice learning opportunity though.
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Old 7th May 2014, 11:32 PM   #5
jcx is online now jcx  United States
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Peranders has changed over to the array of vias for his TPA6120 project amp - but not tented so he can hand solder, feeding from the back

the datasheet, eval board layout recommend cutouts in the power and gnd planes under the -input and trace to the feedback R - this node wants to be very low C I think poured planes are also bad on this - the fringing field capacitance can be higher than you might expect

I discuss output series isolating Z in a few posts, over a few pages : National LME49600 Reference Design Project
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Old 7th May 2014, 11:54 PM   #6
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Quote:
Originally Posted by jcx View Post
Peranders has changed over to the array of vias for his TPA6120 project amp - but not tented so he can hand solder, feeding from the back
I'll have a look. I wonder if I don't already have an alternative library somewhere...

Quote:
the datasheet, eval board layout recommend cutouts in the power and gnd planes under the -input and trace to the feedback R - this node wants to be very low C I think poured planes are also bad on this - the fringing field capacitance can be higher than you might expect
There's no groundplane under the tpa's inputs and tracks towards r23/r24. Do you mean that I should also increase the cutouts in the horizontal plane ?

I'm not familiar with the "fringing field capacitance" and a quick google search didn't turn many useful results out (my google-fu is weakening it seems). Any link ?

Quote:
I discuss output series isolating Z in a few posts, over a few pages : National LME49600 Reference Design Project
Thank you, many useful info in there It seems that the inductors linked earlier would be fine at 2uH. Impedance at 1MHz is above 10r. The datasheet isn't very detailled but a max DC current of 3A gives a nice margin.
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Old 8th May 2014, 09:34 AM   #7
marce is offline marce  United Kingdom
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Look here page 4.2 4.3:
http://www.ti.com/lit/ug/slou169/slou169.pdf

Figure 4 shows fringe and in-plane fields, don't think we really have to worry about this a low frequency of audio analogue signals. RF analogue it can be a problem and with high speed digital as this document shows.
http://home.educities.edu.tw/oldfrie...ced_Jitter.pdf
I was surprised to see this device so sensitive to stray capacitance, its not something you encounter everyday even in the wider world of electronics, though some fast analogue devices you do cut away the planes under the pins (not the traces), but this was a very fast analogue board for testing a fancy sensor.
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Old 8th May 2014, 09:55 AM   #8
marce is offline marce  United Kingdom
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Fringe fields go from the line, or plane edge to the plane below (at the edge, the fringe) in-plane are field lines between adjacent conductive patterns on the same layer.
Via fences are used to help control the field lines for both EMC and RF microwave crosstalk reduction.
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Old 8th May 2014, 10:03 AM   #9
00940 is offline 00940  Belgium
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Thank you, I've been reading the EVM again. There's no bottom groundplane in my layout and the wide PS tracks don't go anywhere under the input pins, so I should be fine. Right ?

One thing I could do is move r13-14 further right (next to the vias going to the + input pins).

Quote:
Originally Posted by marce View Post
I was surprised to see this device so sensitive to stray capacitance, its not something you encounter everyday even in the wider world of electronics, though some fast analogue devices you do cut away the planes under the pins (not the traces), but this was a very fast analogue board for testing a fancy sensor.
If my memory serves me well, the tpa6120 is a rebadged dsl driver. jcx will be able to correct me on this.
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Old 8th May 2014, 10:27 AM   #10
marce is offline marce  United Kingdom
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That would figure, this ADSL driver recommends removing the plane round the pins, page 12, Layout Considerations.
http://www.analog.com/static/importe...ets/AD8019.pdf
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