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Old 3rd June 2013, 10:29 PM   #1
agdr is offline agdr  United States
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Default Massively parallel LME49990 headamp

Here is something you don't see everyday. It occured to me that the desktop amp I've got going on in another thread could be chopped down and massively parallel LME49990's used for the output buffers. The LME49990s are relatively cheap these days at $2.50 each and have great performance, at least on the data sheet.

Going with using 1% of the 24ma maximum output current into 600R for balancing current would be 3.32R or so balancing resistors.

The layout below is just something I threw together quickly to see if it would even fit on a 80x100mm PC board (B2-080 case) and sure enough, looks like it does. 80x100mm gets the cost down enough to go 4 layer, with a groundplane under the LME49990 buffers and a boatload of decoupling caps at the power pins. 12Vac power transformer (wall wart) input so as not to exceed the 20V max on the LT1963A, so +/-12Vdc rails. The circuitry out to the side is the clipping detect circuit which could probably fit under the board.

Still uses two LME49990 chips for the gain stage / bass boost. If someone wanted to go direct DC coupled with no coupling caps in the path the DC offset of the LME49990s is probably low enough. Just leave out the 12 4.7uF film coupling caps in the middle and jumper one set of PCB cap holes on each channel to pass the signal along. Still has a 1K pot in the middle for low Johnson noise, something that wouldn't work if the pot was in front due to source loading.

I don't know if I'll try fabbing it or not, but if one of you layout wizards out there beat me to it I would probably buy a board. I'm curious how it would sound. The data sheet seems to show 0.000005% THD with an 8Vrms swing into 600R with +/-15V rails, for a single chip, if I'm reading that graph correctly. That would be 13mA rms for a single chip. This guy has 8 chips per channel to feed lower impedances.
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Last edited by agdr; 3rd June 2013 at 11:00 PM.
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Old 4th June 2013, 02:43 AM   #2
agdr is offline agdr  United States
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Here is what LT Spice comes up with for the massively parallel LME49990 headamp using TI's LME49990 sim model.

The first plot is with a single LME49990 output buffer feeding a 32R load (green plot, left scale). The blue is the output of the gain stage feeding the 1k pot, also a LME49990, feeding the 1K pot (the 1k attenuation resistor is jumpered). I've run the peak input voltage soure up to the onset of output clipping to find out what the model predicts for the +/-12Vdc supply rails. The red on the righthand scale is the current through one chip's balancing resistor, the per-chip current.

The results match up very well with the datasheet, which lists a worst case output voltage swing of 12Vdc with +/-15Vdc rails 3Vdc down from the rails), powering a 600R load. Here with 12V rails we can extrapolate to a max swing of around 12 - 3Vdc -9Vdc. The sim shows clipping out of the gain stage, with the 1k load at about 8.2Vdc. The single chip output into the 32R clips at 2.4V, a gallant try! The sim parameters are in the plot names, 20kHz 3.45Vpeak input in this case.

Now with the 8 output chips in parallel the sim plot looks amazingly good. The output of the 8 chips is clipping just slightly behind the gain stage at 8.0 and 8.2 respectively. But - is there smoke coming out? 8V peak would be 5.6Vrms, leaving about 6.4Vrms across each chip. The per-chip current is 32mA peak or 22.6mA rms. The dissipation in the chip is then 5.6Vrms x 22.6mA rms = 126mW, if I've done that right, which should be within the dissipation profile for the package including quiescent. So no smoke.

But the total dissipation over the 8 chips is 8 x 126mW = 1watt! 2 watts total over both channels (16 chips).

The next plot is the 8 buffer 32R load (plus 390pF in parallel on all these for cable capacitance) but at 10Hz to check that the 6 caps coupling caps on each channel are doing their thing. The simulation doesn't like to converge at low frequencies with clipping so I've had to back the input voltage down to 3.0V from 3.45 for convergence, but note that at 3.0V there is no clipping yet. Things at 10Hz are working as they should be.

The final plot is the power supply using the LT1963A and LT3015 sim models. Predicts about 4mV of ripple with a 200mA per channel load, well within the PSRR of the LME49990 chips to deal with. The bottom of the ripple sawtooth is about 1.5Vdc above the output voltage, and the LDOs only needs about 0.5Vdc drop, so that leaves about a volt of wiggle room for power mains fluctuations (about +/-10Vac back on the primary side).

Last edited by agdr; 4th June 2013 at 02:56 AM.
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Old 4th June 2013, 02:48 AM   #3
jcx is offline jcx  United States
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the heaviest load in headphones I know of are the hifiman orthos - if you take clipping free 120 dB SPL as a audiophile amp goal then 6 Wrms are required into 50 Ohms

requiring ~ 25 Vpk, 500 mApk ampltude

bridged parallel op amps could get you there - my cascaded, paralleled TPA6120 with 6x op aqmps per channel can do it

bridged, the TPA6120 would only require 2x parallel - and give considerable current reserve

I use a multiloop with OPA627 feedback wrapped around the TPA - which are also delivering V gain inside the loop, further linearizing the input op amp by requiring less
Vswing as well as buffering the load

the TPA chips have TI's power pad for external heatsinking

the TPA6120 are way cheaper per W, per mA output
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Old 4th June 2013, 03:04 AM   #4
agdr is offline agdr  United States
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jcx - the TPA6120 is a good chip! 0.0001% THD into 600R load if I'm reading the sheet correctly. But that would be lower with your loop around the chip. The only hiccup is that required 10R output resistor for stability, but that is a moot point for higher impedance phones and probably a lot of lower impedance cans. If you've paralleled them that effective output impedance looking back into the port is probably lower too. Good design!

Last edited by agdr; 4th June 2013 at 03:11 AM.
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Old 4th June 2013, 03:24 AM   #5
jcx is offline jcx  United States
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Default Cload isolation needed with amost any 100 MHz op amp/buffer

unless the data sheet specificially calls out "C-Load Stable"

LME49990 datasheet:
Quote:
Capacitive loads greater than 100pF must be isolated from
the output. The most straight forward way to do this is to put
a resistor in series with the output. This resistor will also prevent
excess power dissipation if the output is accidentally
shorted.
so that really isn't a differentiating feature - except for the lack of guidance with the LME on the value of series R - they do show a recommended load network


there's no difficultly using series L to decouple Cload - could be air core, toroid if you really worried about magnetics linearity
the L can be small since it only has to reach |10-20| Z in the 10s of MHz

I use lossy ferrite smt bead with I rating 5-20x the op amp capabillity - haven't seen any distortion when measuring with ESI Juli@ yet

Last edited by jcx; 4th June 2013 at 03:41 AM.
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Old 4th June 2013, 03:44 AM   #6
agdr is offline agdr  United States
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jcx - good point! I did see that 100pF load issue and figured the 3.32R on each chip would go some distance toward isolating it, but like you say they really don't give any guidelines. And the spice sim would be useless for something like that. Would just have to build it an do a bunch of measuring with various loads.

They also list that under the "stability" heading, then spend their time talking about settling time, like it is more of a transient response or overshoot issue, which is a common result of load C.

In fact, there is a question I'll bet you would know the answer to. I was pondering this one this afternoon and couldn't figure it out. If a single chip is rated to directly drive 100pF, then would 8 in parallel (with the balancing resistor) drive 800pF? From a step response standpoint I'm thinking the answer is probably "yes", since there would be 8x the current sink/source ability to charge/discharge the cable capacitance. But from an AC standpoint, S plane, I'm thinking the answer is probably "no" from a stability standpoint. Thoughts?
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Old 4th June 2013, 03:58 AM   #7
jcx is offline jcx  United States
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offhand I'd guess that paralleled "hot" op amps that already have the Cload problem to begin with do take a stability hit if the summing R are really small - especially with V feedback operating with low phase margin at unity gain

the classic op amp output model of a series R with 90 degree phase margin dominant loop compensation already looks inductive at the gain intercept, must tip over into negative Z with reduced phase margin


CFA can be “over compensated” by just increasing the feedback R, accepting a little less BW
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Old 4th June 2013, 04:25 AM   #8
agdr is offline agdr  United States
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Quote:
Originally Posted by jcx View Post
CFA can be “over compensated” by just increasing the feedback R, accepting a little less BW
That is another good thing about the TPA6120. Would the equivalent thing for a VFA be to bridge the inputs with some resistance, or resistance + series C, to add phase lead?

I'm curious, have you tried wrapping an LME49990 around a TDA6120 instead of the OPA627? The AC specs look better, I think, if there isn't an absolute need for the FET inputs.

Last edited by agdr; 4th June 2013 at 04:34 AM.
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Old 4th June 2013, 06:12 AM   #9
jcx is offline jcx  United States
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my suspicion is that fet input purported superior EMI immunity would be a winning proposition over pushing distortion to sub ppm

besides I really do better than the OPA627 datasheet THD with the added CFA gain inside the loop, my particular multiloop tricks
couldn't measure any 1 kHz diff IMD with 10 kHz+11 kHz 1:1, added 30 dB gain stage, 100 s average with ESI Juli@ - 160 dB resolution
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Old 4th June 2013, 01:39 PM   #10
agdr is offline agdr  United States
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Yeah, I agree, there comes a point with the distortion where it just simply isn't going to be audible anymore. Just pushing lower numbers just for numbers sake. That is interesting about the FET EMI immunity, I hadn't heard about that. I'll have to do some Googling.
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