J-Mo Mk II headphone amplifier

[rjm]

Status: concept stage.

Prior art: this and this and tangentially to this.

Current activity: doing it up in ltspice, confirming operating points, circuit values, components, etc.

[rjm]

LTSpice simulation progressing well. To design using Spice is not my thing, but for optimizing the operating points and debugging creations, it's pretty great.

This circuit topology is terribly inefficient, you have to bleed for output power. What really adds insult to injury here though is the 4 V turn on voltage of the IRF510. This is the main reason that a 12 V voltage rail only gets you 1.4 V max output (<4 V p-p).

I could get around this by using a 2SK213. Maybe, I haven't checked recently to see if my source still have them. The thing is, all the nice Toshiba audio MOSFETs are obsolete. It's all switching applications now, and most of those are SMT. The IRF510, with it's low input capacitance, still seems like the best option when availability of factored in.

(perhaps also Vishay Siliconix IRLIZ14G)

[rjm]

LTSpice file attached, if you want to follow along at home.

[rjm]

A digression from LT Spice to Excel for a moment.

It's not too hard to plot up a quick and dirty model for the circuit behavior, and the results give a nice visual indication of what's going on.

The output power of this circuit is typically determined by the source voltage, the source resistance, and the load resistance (headphone impedance). For the rest it's just a matter of setting the voltage rail (V+) high enough to avoid clipping before the maximum output current is reached.

So then it comes down to what output power into what headphone load is desired, and what level of heat dissipation will be tolerated.

As an aside, this circuit will work very nicely with high impedance headphones, but will not work very nicely with both high and low impedance headphones. The circuit values can be optimized for one or the other, but sadly not both.

I am concentrating here on low impedance phones, 16 ohms especially as these seem very common these days.

The design center values (i.e. what I'm hoping to obtain in the real circuit) are >100 mW output into 16 and 32 ohm headphones and about 2-3 watts of heat. I'd also like to avoid voltage clipping even for 300 ohm headphones, the maximum possible output power is obtained there, too.

The worksheet is pointing to Rs 33 ohms, Vs 5.5 V, V+ 20 V, and a standing power dissipation of 2.8 W per channel.

The V+ is higher than I originally planned, but the heat is within budget. I will refine the circuit gain to match these new operating points and feed it back into LT Spice.

[rjm]

LT spice agrees nicely with the worksheet estimates.

Working through it, I realized that it might be possible to get rid of the voltage divider on the input: if the gain is increased a little, to about 12 dB, the natural source resistor bias of the JEFT puts the MOSFET gate at the right voltage.

That puts you at the mercy of the jfet to set the operating points however.

[rjm]

Been using LTSpice to get a better handle on how the front end of the circuit works.

Given a JFET-PNP pair, I can configure the desired gain. There is a lot of inter-dependency though, as a result of the feedback and the complication that here the AC gain sets the DC operating points. (!) There doesn't seem to be a need for an input bias, as long as the gain needed to correctly set the operating point also happens to be one you can live with for the audio signal gain, too. Fortunately this is largely true, as long as the JFET model can be chosen freely to match the desired signal gain.

So I need to settle what JFET would be best to use, and, of lesser importance, which transistor. Or to put it another way, how much current do I really need to send down the input stage, and how should I split the currents between JFET and PNP devices?

By the way, I rather like this JFET-PNP compound device. The gain is highly configurable between 1-10 (100?), and the bandwidth in excess of 1 MHz. I could imagine using it in a phono stage, with a second JFET replacing the output MOSFET.

Ideas ideas...

[rjm]

Up and running under simulation.

Gain 5.5x (15 dB), bandwidth ~1 Mhz, pushing just over 4 V p-p into a 16 ohm load, or over 11 V p-p into 300 ohms.

This is just before the onset of hard current clipping, the negative waveform is already heavily distorted (2nd harmonic) in both cases.

R3 adjusts the current through the JFET and hence the bias voltage across R4 which in turn fixes the MOSFET operating point. It can be made a 10k trim pot to allow full adjustment and channel matching.

P.S. Everything is ticking over quite smoothly. My only concern at this point that for low circuit gains of 3x or 4x the JFET gate-source voltage has to be fairly high, about 2 V, to lift the MOSFET gate up to the 9.5 V required. This generally means operating the JFET at an atypically low I_ds.

P.P.S. PSRR is 40 dB at 120 Hz, still 34 dB at 20 kHz. Not bad, considering it's a simple single supply circuit. Some sort of RC or LC filter stage or voltage regulation will be required. V+ ripple will need to be under 100 mV to avoid audible hum.

[rjm]

This circuit isn't quite "build-and-go", the circuit values are worked out as follows. The main issue is that multiple resistance values have to be optimized for a particular JFET. A near substitution of JFET model can probably be cleared just by trimming R3, but there is a risk of inadvertently choking off the current to the pnp transistor if R3 is set too small without changing R4 and R6 to compensate.

1. Choose the output stage operating bias and V+, defined by Vs and Rs, depending on the desired output power, headphone load, and thermal budget.

-> Vs 5.5 V, Rs 30 ohms, and ~~ 3W for V+ 20V.

2. Mosfet gate is Vs + 4 V = 9.5 V. The input stage gain x the JFET source bias voltage must equal 9.5 V.

-> JFET source bias can be from 0-Vturnoff. Choose a highish current JFET like the J111 with a high Vturnoff, so that he gain doesn't have to be to high to bring the output up to 9.5 V.

3. The J111 (and similar with Vturnoff 2.5 V - 3 V) seem to run about 1 mA at a source bias of about 1.8 V - 2 V. The current through the pnp transistor Q2 should be 2 mA or higher or more to make sure there it has enough control to keep everything working as designed.

-> This means that R3 is about X, and, to keep the gain and transistor currents in the right ballpark, R4 should also about X and R6 is about 5X. First roughtly estimate X based on the JPEG used, for the J111 it's about 680-950 ohms. After setting R4 and R6 from this estimate, the final tuning of the operating points can be done by trimming R3.

The J111 seems like a widely available model, so we'll run with that. Any n-channel JFET with Vturnoff of around 3 V should be able to be substituted. Using a smaller Vturnoff JFET is possible but R4,R6 will have to be adjusted to increase the gain since the JFET bias is not going to go much above 1 V.

[rjm]

So, short story is this circuit is going to need well-matched pairs of JFETs. Which means buying 10 and picking the best 2.

Attached is a visualization for what to expect when buying 2N5484-5-6 series of parts. These are all the same JFET, just binned by the manufacturer depending on how they test.

Green circles indicate roughly the "most likely the part will measure somewhere in here" area.

Now, for the desired gain of 5-6x, and MOSFET gate of 9.5 V, the Vgs operating point should be about 1.5-1.8 V, and we are hoping for about 1 mA, so the target specifications are a Vd of 3-3.5 V and Idss of 5 mA. This is unliklely to be found for either the 2N5484 or 2N5485 parts. So either I compromise or look for another JFET.

Right now I'm thinking the 2N5485 looks pretty good, chances good of finding a couple around Vd = 2.5 V and Idss = 8 mA. That should be workable.

[regal]

What I always like about the original was the unity gain without feedback, made a nice transparent substitute for an expensive OPT (hybrid tube amp.)

Always want to try and run complimentary with split supply and possibly eliminate the output cap, increase the input impedance so the input cap could be smaller less load on the tube.

Thanks for the update and the model.