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Old 3rd March 2012, 06:52 AM   #31
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I started to explore how to do all (or most) of the necessary calculations in the thread at paralleling film caps with electrolytic caps
Jerald Graeme does just this in Ch.3 of his book Optimizing Op Amp Performance. It's a high-level book (ie he didn't write it for a knucklehead like me) but I can give the formulae he derived:
For the primary bypass cap Cb = 50/pi*fc
"Here fc represents the unity-gain crossover frequency of the op amp and generally represents the upper limit of the amplifier's useful frequency range."
For the secondary bypass cap Cb2 = Lbp1
"Thus simply making the magnitude of the Cb2 capacitance equal to that of Cb1's parasitic inductance transfers line impedance control from Zcb1 to Zcb2 at the 1-ohm level."
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Old 3rd March 2012, 07:50 AM   #32
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Originally Posted by nezbleu View Post
I would not use a 16V-rated cap on a 15V rail, I think that is asking for trouble. You want at least a 25V part there. I second the Pana FM/FR recommendation.
With tantalums you want to stay FAR away from the rated Voltage. When they fail they go dead short and if the supply has enough capacity, the cap will explode. Go check John Larkin's tantalum experiences in

*gasp* Useful EDN article on tantalum caps - sci.electronics.design | Google Groups

John's company is Highland Technologies in San Francisco.

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Old 3rd March 2012, 02:02 PM   #33
gootee is offline gootee  United States
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Originally Posted by sofaspud View Post
Jerald Graeme does just this in Ch.3 of his book Optimizing Op Amp Performance. It's a high-level book (ie he didn't write it for a knucklehead like me) but I can give the formulae he derived:
For the primary bypass cap Cb = 50/pi*fc
"Here fc represents the unity-gain crossover frequency of the op amp and generally represents the upper limit of the amplifier's useful frequency range."
For the secondary bypass cap Cb2 = Lbp1
"Thus simply making the magnitude of the Cb2 capacitance equal to that of Cb1's parasitic inductance transfers line impedance control from Zcb1 to Zcb2 at the 1-ohm level."
That is interesting, too. It's a different focus than I was taking, since it's about bypassing more than decoupling. But it looks like he might be taking many or most of the same things into account.

I haven't read Graeme's stuff, yet. I had received Henry Ott's EMC book just after I started the decoupling explorations at the link I gave, so I drew heavily on his work and on some others found on line. They are all mainly worried about high-frequency digital circuits on multi-layer PCBs but I tried to apply their methods (and some very-basic math) to high-current audio amplifier circuits on one or two sided PCBs (or point-to-point), with mainly through-hole/leaded parts, since that is what most DIYers can implement most easily, and also seems more-likely to be difficult to get right.

Interestingly, the equation from Graeme that you gave, Cb = 50/pi*fc, looks closely-related to an equation that Ott provided for bandwidth versus rise time, i.e. f = 1 / (π trise), which can be rearranged as trise = 1 / (π f), which is very similar to Graeme's 50 / (π f), implying that he uses Cb = 50 x trise. I'm not sure how the physical "units" work out, there, without seeing how he got the "50". But it's interesting.

Ott basically started with the worst-case current range that would need to be slewed through (call it dI), along with a chosen maximum rail-voltage disturbance (call it dV) to try to have, and the worst-case (shortest) rise time (call it dt) based on the max slew rate. With those, you can find a "target impedance" across the decoupling points, Zt = dV / dI, which must not be exceeded up through at least the frequency implied by f = 1 / (π trise).

That gives enough constraints to solve for C in two different ways and we can just use the larger result:

C ≥ 1 / (2 π f Zt) (from the standard capacitor impedance equation)

and

C ≥ dI dt / dV (from the standard differential equation for capacitor behavior)

So far, the parasitic inductance problems have been left out. But since V = L dI/dt (the standard inductor equation), I think that we can use our previously-established dV, dI, and dt and find that

L ≤ dV (dt / dI)

is the maximum total inductance that can be tolerated, in the decoupling capacitance plus its connections.

(That's not quite the whole story, so please see the posts indicated, at the link I gave, if interested.)

For an example with 10 Amps in 2 μs, with 0.1 Volts or less rail-disturbance amplitude, that comes out to needing L ≤ 20 nH, which is on the order of one inch of combined trace/wire length plus capacitor lead spacing, maximum!

That could be very difficult to implement on a one- or two-sided PCB with an LM3886 layout, especially since the capacitance would be at least 200 uF or more, for that example.

So, for practical DIY applications, the main problem to solve seemed to have become finding ways that could be used to "get around" the parasitic inductance problem.

Obviously, a professional PCB designer would immediately decide to use multi-layer boards with separate power and ground planes. And we could DIY several versions of that, by using thin PCB laminates and gluing them together (which I am going to try, since the ease-of-layout benefits would also be so great). But I also wanted to see how far we could get with the easiest and more-traditional DIY construction types.

One way to get lower inductance is to use several smaller decoupling caps in parallel. But note that the total inductance won't fully reduce (like total resistance reduces when paralleling resistors) UNLESS there is no mutual inductance, which, I think, means that the connections could not share conductors, i.e. the connections would also have to be paralleled, all the way to the decoupling points if possible (which would be much easier with power/gnd planes, but is also why even with planes the cap placement geometries do matter, as does the distribution geometry for injecting power into the power planes, i.e. the currents should ideally use separate paths, on the planes, so there is less mutual inductance involved).

An extension of that might be to use multiple parallel power and ground rails, all the way from the PSU to the device, with each set of filter and decoupling capacitances basically having their own pair of power/ground rails. That seems like a very promising approach and is where I have gotten, so far (having been interrupted by demands from my real job and some other stuff).

That approach should be able to give one of the main benefits of power and ground planes, but when using simple PCBs or point-to-point wiring. Theoretically, we would be able to make the PSU impedance, as seen by the device pins, as small as desired, by adding more parallel paths from the PSU to the device, since the total parasitic inductance and parasitic resistance would be divided by the number of conductor pairs that were used, while the total filter and decoupling capacitances would be multiplied by the number of conductor pairs that were used. There will probably be limits that appear quickly for practical implementations. But at least all of the variables we were worried about move in the right directions.

Sorry to have blathered-on for so long about all of that. I don't want to take this thread too far away from what the OP intended. Maybe we can consider an LM3886 to be an overgrown opamp
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Last edited by gootee; 3rd March 2012 at 02:22 PM.
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Old 5th March 2012, 07:09 AM   #34
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Originally Posted by ClaveFremen View Post
They sound pretty good but after sometime I always swap them with other caps, they sound somewaht confused.
Interesting... Actually I've soldered two nichicon KZ 220uF 25V directly to opamp power pins in my XONAR STX buffer, I found the result very nice, warm and detailed, with deep and strong bass

But I have a couple of those old stilish big cerafine 1000uF 35V around, I'm tempted to swap nichicon for these
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Old 8th March 2012, 02:54 AM   #35
gootee is offline gootee  United States
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Originally Posted by robyonekenoby View Post
Interesting... Actually I've soldered two nichicon KZ 220uF 25V directly to opamp power pins in my XONAR STX buffer, I found the result very nice, warm and detailed, with deep and strong bass

But I have a couple of those old stilish big cerafine 1000uF 35V around, I'm tempted to swap nichicon for these
Or you could try replacing each of the 220 uF caps with two 100 uF or three 68 uF or four 47 uF or 56 uF, etc.

The more caps you can fit in parallel, physically, the better it should be, since the overall ESL (equivalent series inductance) and probably also the overall ESR (equiv ser resistance) should be divided by the number of paralleled caps that are used, especially if their leads share as little conductor length as possible (except don't incur too much extra lead or conductor length trying to achieve that).

And if the smaller caps have a smaller LS (lead spacing), then they should start out with lower inductance (than the larger original cap) and the benefit should be even greater.

Last edited by gootee; 8th March 2012 at 02:56 AM.
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Old 8th March 2012, 06:59 AM   #36
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This method could be right just to reduce ESL, not the ESR

The smaller (physically) the cap, the higher the ESR, so paralleling more smaller caps doesn't give any real advantage about ESR

But it does about ESL, because while the ESR is inversely proportional to cap dimension, the ESL is directly proportional
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Old 8th March 2012, 07:13 AM   #37
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The ESR's are in parallel, which effectively reduces the total resistance. I'm under the impression that some resistance can be beneficial as it dampens the LC resonance.
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Old 9th March 2012, 03:01 AM   #38
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Originally Posted by robyonekenoby View Post
This method could be right just to reduce ESL, not the ESR

The smaller (physically) the cap, the higher the ESR, so paralleling more smaller caps doesn't give any real advantage about ESR

But it does about ESL, because while the ESR is inversely proportional to cap dimension, the ESL is directly proportional
I have to agree. The ESL is much more important here. And I was trying to emphasize the ESL, originally. But I threw in the ESR at the last minute. I did try to hedge a little about the ESR, because there are two competing effects, making it unclear (to me, at the time) whether or not there would always be a beneficial effect on the ESR. Basicaly, I just didn't stop to think about it for quite long enough, before adding the ESR to my statements. I wish I had just left it out since it's a less-important parameter, here, anyway, and is now sort-of clouding the issue. But thanks for pointing out the error.
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