Thanx jcx, that must be the reason. I should had looked http://www.analog.com/static/imported-files/application_notes/AN-940.pdf page 8 before.. It shows clearly that OP27 is more suitable for 1-10kOhm impedances and AD797 suits for very low input impedances..
May I ask you why you would avoid nichicon KZ?
I used them for ps decoupling on the buffer opamp in my xonar stx, though they are good value
From what I have read, I think that ClaveFremen probably knows very well, from experience. And remember that the decoupling caps, and the power supply rails, _ARE_ "the signal path". They are what provide the current that produces the actual sound, after all. The decoupling caps are very important for the accuracy of the fast transients, and the PSU rails handle most of the rest. SHORT connections are needed for the decoupling caps, which also help to prevent high-frequency instability. You need some large-ish caps for decoupling, sized to be able to handle the worst-case transient current (maybe use max slew rate 0-to-rail to calculate minimum cap values and maximum lead-spacing+connection inductances; see my previous post). But to help prevent high-frequency instability, you probably ALSO need a lower-inductance path than can be achieved with the larger caps (because of their relatively-large lead spacing and the difficulty in close-to-device placement due to their size), so you probably ALSO need some very-small-size (physical lead-spacing size) caps, right across the power pins or from each rail to load ground (depending on device types and circuit topology), with minimum lead spacing and the shortest-possible total connections' lengths to the decoupling points.
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Hi gootee, yes I agree completely, I know very well the story from my first hand experience
I use to solder decoupling caps right to the opamp pins and connect the cap negative lead to ground via thick wires as short as possible
But about nichicon KZ, I'm interested to read Clave opinion because in my system it seem to perform very well, and also why he prefer the lower grade cerafine to the silmic II
The common opinion is just the opposite
I use to solder decoupling caps right to the opamp pins and connect the cap negative lead to ground via thick wires as short as possible
But about nichicon KZ, I'm interested to read Clave opinion because in my system it seem to perform very well, and also why he prefer the lower grade cerafine to the silmic II
The common opinion is just the opposite
That doesn't make them part of the signal path, per se. Not in anything that has non-zero PSRR. While it is obviously important to keep output stage current pulses from "talking back" into previous stages at high frequencies (which would generate distortion), the high OLG and GBW of common opamps mean that requirements are a lot more relaxed at lower ones.
Besides, supply rails tend to be approximately constant. That's how you can get away with using ceramic (X7R) decoupling caps in spite of them being appreciably nonlinear - their low ESR has them drain any kind of supply ripple straight to ground, with very little of it dropping across the capacitor. Their change of capacitance with voltage thus doesn't do any harm, and their low ESR is beneficial.
It also follows that supply decoupling requirements are stricter with increasing output current (as you'd expect anyway).
Using a low-ESR electrolytic and a decoupling cap directly in parallel can be troublesome, as the parasitic inductance of the electrolytic may form a parallel LC circuit with the decoupling cap and give a high-impedance peak somewhere. As long as their capacitance values are not more than 2 to maybe 3 orders of magnitude apart, this usually isn't that much of a problem, but I'd be careful with a 1000(+) µF + 100 nF combo.
Trace inductance could do the same, btw, another reason to keep loop area small.
They sound pretty good but after sometime I always swap them with other caps, they sound somewaht confused.
As I have mentioned somewhere before, it appears that you are thinking mostly only in terms of the VOLTAGE of the supply rail. But the CURRENT is the signal, in the power and ground rails.
Also, the electrolytic IS the main decoupling capacitor, at audio frequencies, especially for a power amplifier. The other much-smaller parallel cap is for high-frequency bypass and decoupling, but probably mainly just for bypass in a lower-frequency circuit such as audio, since there aren't any MHz or GHz risetimes to worry about decoupling and we probably only need those small caps to prevent HF instabilities by shorting-out (bypassing) the "hidden" feedback path (between power rails and input), for high frequencies.
So yes, in fact, the audio's fast transients are directly provided by the large decoupling capacitors, straight through the output transistors and directly to the speaker. And the slower stuff and the steady-state stuff is mostly provided by the filter caps, similarly directly to the speaker.
One could argue that the decoupling and filter caps _ARE_ the main signal path (since they are). All of the rest of the small-signal "signal path" portions of a power amplifier only indirectly control the signal to the speakers, by controlling the current valves that we call "output stage transistors".
Anyway, of those two (decoupling caps and filtering caps), the decoupling caps seem to be more susceptible to affecting sound quality due to sub-optimal implementation, which is why I worry more about the decoupling caps. Lots of people tend to use plenty of filter capacitance. And the power rails' configuration isn't as critical, for those, since they can usually only supply the slower-changing audio output currents (mainly because of rails' inductances). So most people seem to get their filter caps working well-enough.
But decoupling capacitors seem to be less well understood and typically less-well-executed. Or at least I understood them less well. Anyway, I have found that the decoupling caps for many audio power amplifiers can fairly-easily be implemented in ways that limit the potential performance of the amplifier. They must have a large-enough capacitance value to meet the worst-case transient current demand (while limiting rail-voltage disturbance to a chosen maximum amplitude). And they AND their connections must have a low-enough total inductance when connected to where the transient current demands must be met, if the transients are to be accurately reproduced (amplitude vs time).
I started to explore how to do all (or most) of the necessary calculations in the thread at http://www.diyaudio.com/forums/power-supplies/106648-paralleling-film-caps-electrolytic-caps.html . Look at posts 221 and 224, with some more in post 252, which led me to do posts 310-314 and 319, and 341.
I do agree that there can be problems when paralleling an electrolytic and a relatively-small cap. But the ESR of the electrolytic isn't usually the problem. Even the "low-ESR" types do not have extremely-low ESR. The small cap's ESR, on the other hand, CAN be a potential problem, such as when a film cap is used there. With its tiny ESR, its capacitance can form an under-damped HF resonance with any stray inductance, such as that of the electrolytic.
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Why is it then that TI in their recommendations for the TPA6120A and formerly Nat Semi in their recommendations for the LME49600 (both headphone drivers) both recommend a combination of SMT tants and MLCC for supply bypassing?
Many of the caps under discussion are leaded devices with their accompanying lead inductances. TH caps in any case are outperformed by SMD for bypassing.
Quote:-
For example, the LME49600’s output voltage can slew at a typical ±2000V/μs. When driving a 100Ω load, the di/dt current demand is 20 A/μs. This current flowing through an inductance of 50nH (approximately 1.5” of 22 gage wire) will produce a 1V transient. In these and similar situations, place the parallel combination of a solid 5μF to 10μF tantalum capacitor and a ceramic 0.1μF capacitor as close as possible to the
device supply pins.
'as close as possible to the device supply pins' means to me 'put the via in the pad.' Attention paid to this kind of detail will, IMO, yeild a better payoff than endlessly seeking 'the best caps for audio'. I'm not denying that caps can affect the sound, but alum. electrolytics used for coupling purposes, not power supply bypass.
Not that I want to start a furore, but somebody has to put the opposing point of view.
Many of the caps under discussion are leaded devices with their accompanying lead inductances. TH caps in any case are outperformed by SMD for bypassing.
Quote:-
For example, the LME49600’s output voltage can slew at a typical ±2000V/μs. When driving a 100Ω load, the di/dt current demand is 20 A/μs. This current flowing through an inductance of 50nH (approximately 1.5” of 22 gage wire) will produce a 1V transient. In these and similar situations, place the parallel combination of a solid 5μF to 10μF tantalum capacitor and a ceramic 0.1μF capacitor as close as possible to the
device supply pins.
'as close as possible to the device supply pins' means to me 'put the via in the pad.' Attention paid to this kind of detail will, IMO, yeild a better payoff than endlessly seeking 'the best caps for audio'. I'm not denying that caps can affect the sound, but alum. electrolytics used for coupling purposes, not power supply bypass.
Not that I want to start a furore, but somebody has to put the opposing point of view.
older sintered Ta caps had fairly reliable esr suitable for damping supply resonance, small package gave superior low parasitic inductance
modern smt electros can have too small esr for good damping - can destabilize Vregs when put on the output
high value ceramic caps can have even higher Q
actually designing power supply/load/return impedance today may involve deliberate series damping R or lossy ferrites
for most audio apps we will have series load decouping Z to prevent instability with long cable Cload - this interrupts the ps/chip amp/load/return loop at very high frequencies
modern smt electros can have too small esr for good damping - can destabilize Vregs when put on the output
high value ceramic caps can have even higher Q
actually designing power supply/load/return impedance today may involve deliberate series damping R or lossy ferrites
for most audio apps we will have series load decouping Z to prevent instability with long cable Cload - this interrupts the ps/chip amp/load/return loop at very high frequencies
Well I, for one, totally agree with you, counter culture.
For decoupling, the shortest connections are the best and surface mount will give the shortest connections.
Through-hole (without PCB planes) is where it can get "interesting", and often impossible, actually, especially for fast high-current amplifiers, since "shortest" might not be "short-enough", unless one resorts to paralleling multiple smaller-value caps and makes sure that even the connections are paralleled right up to the points needing decoupling, to get the lowest inductance. It's a lot of work to figure out how it would need to be done and a lot of work to make a layout to accomplish it. And people would have to first realize that it was necessary or beneficial.
People seem to often chase after the wrong grail, without first finding out how its significance compares with other things they could have chosen to worry about first, maybe because it would take a LOT of hard work to find out. But that's one excellent reason for sharing any knowledge that took a lot of work to acquire, as you have just done.
For decoupling, the shortest connections are the best and surface mount will give the shortest connections.
Through-hole (without PCB planes) is where it can get "interesting", and often impossible, actually, especially for fast high-current amplifiers, since "shortest" might not be "short-enough", unless one resorts to paralleling multiple smaller-value caps and makes sure that even the connections are paralleled right up to the points needing decoupling, to get the lowest inductance. It's a lot of work to figure out how it would need to be done and a lot of work to make a layout to accomplish it. And people would have to first realize that it was necessary or beneficial.
People seem to often chase after the wrong grail, without first finding out how its significance compares with other things they could have chosen to worry about first, maybe because it would take a LOT of hard work to find out. But that's one excellent reason for sharing any knowledge that took a lot of work to acquire, as you have just done.
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Jerald Graeme does just this in Ch.3 of his book Optimizing Op Amp Performance. It's a high-level book (ie he didn't write it for a knucklehead like me) but I can give the formulae he derived:
For the primary bypass cap Cb = 50/pi*fc
"Here fc represents the unity-gain crossover frequency of the op amp and generally represents the upper limit of the amplifier's useful frequency range."
For the secondary bypass cap Cb2 = Lbp1
"Thus simply making the magnitude of the Cb2 capacitance equal to that of Cb1's parasitic inductance transfers line impedance control from Zcb1 to Zcb2 at the 1-ohm level."
With tantalums you want to stay FAR away from the rated Voltage. When they fail they go dead short and if the supply has enough capacity, the cap will explode. Go check John Larkin's tantalum experiences in
*gasp* Useful EDN article on tantalum caps - sci.electronics.design | Google Groups
John's company is Highland Technologies in San Francisco.
G²
That is interesting, too. It's a different focus than I was taking, since it's about bypassing more than decoupling. But it looks like he might be taking many or most of the same things into account.
I haven't read Graeme's stuff, yet. I had received Henry Ott's EMC book just after I started the decoupling explorations at the link I gave, so I drew heavily on his work and on some others found on line. They are all mainly worried about high-frequency digital circuits on multi-layer PCBs but I tried to apply their methods (and some very-basic math) to high-current audio amplifier circuits on one or two sided PCBs (or point-to-point), with mainly through-hole/leaded parts, since that is what most DIYers can implement most easily, and also seems more-likely to be difficult to get right.
Interestingly, the equation from Graeme that you gave, Cb = 50/pi*fc, looks closely-related to an equation that Ott provided for bandwidth versus rise time, i.e. f = 1 / (π trise), which can be rearranged as trise = 1 / (π f), which is very similar to Graeme's 50 / (π f), implying that he uses Cb = 50 x trise. I'm not sure how the physical "units" work out, there, without seeing how he got the "50". But it's interesting.
Ott basically started with the worst-case current range that would need to be slewed through (call it dI), along with a chosen maximum rail-voltage disturbance (call it dV) to try to have, and the worst-case (shortest) rise time (call it dt) based on the max slew rate. With those, you can find a "target impedance" across the decoupling points, Zt = dV / dI, which must not be exceeded up through at least the frequency implied by f = 1 / (π trise).
That gives enough constraints to solve for C in two different ways and we can just use the larger result:
C ≥ 1 / (2 π f Zt) (from the standard capacitor impedance equation)
and
C ≥ dI dt / dV (from the standard differential equation for capacitor behavior)
So far, the parasitic inductance problems have been left out. But since V = L dI/dt (the standard inductor equation), I think that we can use our previously-established dV, dI, and dt and find that
L ≤ dV (dt / dI)
is the maximum total inductance that can be tolerated, in the decoupling capacitance plus its connections.
(That's not quite the whole story, so please see the posts indicated, at the link I gave, if interested.)
For an example with 10 Amps in 2 μs, with 0.1 Volts or less rail-disturbance amplitude, that comes out to needing L ≤ 20 nH, which is on the order of one inch of combined trace/wire length plus capacitor lead spacing, maximum!
That could be very difficult to implement on a one- or two-sided PCB with an LM3886 layout, especially since the capacitance would be at least 200 uF or more, for that example.
So, for practical DIY applications, the main problem to solve seemed to have become finding ways that could be used to "get around" the parasitic inductance problem.
Obviously, a professional PCB designer would immediately decide to use multi-layer boards with separate power and ground planes. And we could DIY several versions of that, by using thin PCB laminates and gluing them together (which I am going to try, since the ease-of-layout benefits would also be so great). But I also wanted to see how far we could get with the easiest and more-traditional DIY construction types.
One way to get lower inductance is to use several smaller decoupling caps in parallel. But note that the total inductance won't fully reduce (like total resistance reduces when paralleling resistors) UNLESS there is no mutual inductance, which, I think, means that the connections could not share conductors, i.e. the connections would also have to be paralleled, all the way to the decoupling points if possible (which would be much easier with power/gnd planes, but is also why even with planes the cap placement geometries do matter, as does the distribution geometry for injecting power into the power planes, i.e. the currents should ideally use separate paths, on the planes, so there is less mutual inductance involved).
An extension of that might be to use multiple parallel power and ground rails, all the way from the PSU to the device, with each set of filter and decoupling capacitances basically having their own pair of power/ground rails. That seems like a very promising approach and is where I have gotten, so far (having been interrupted by demands from my real job and some other stuff).
That approach should be able to give one of the main benefits of power and ground planes, but when using simple PCBs or point-to-point wiring. Theoretically, we would be able to make the PSU impedance, as seen by the device pins, as small as desired, by adding more parallel paths from the PSU to the device, since the total parasitic inductance and parasitic resistance would be divided by the number of conductor pairs that were used, while the total filter and decoupling capacitances would be multiplied by the number of conductor pairs that were used. There will probably be limits that appear quickly for practical implementations. But at least all of the variables we were worried about move in the right directions.
Sorry to have blathered-on for so long about all of that. I don't want to take this thread too far away from what the OP intended. Maybe we can consider an LM3886 to be an overgrown opamp.
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Interesting... Actually I've soldered two nichicon KZ 220uF 25V directly to opamp power pins in my XONAR STX buffer, I found the result very nice, warm and detailed, with deep and strong bass
But I have a couple of those old stilish big cerafine 1000uF 35V around, I'm tempted to swap nichicon for these
Or you could try replacing each of the 220 uF caps with two 100 uF or three 68 uF or four 47 uF or 56 uF, etc.
The more caps you can fit in parallel, physically, the better it should be, since the overall ESL (equivalent series inductance) and probably also the overall ESR (equiv ser resistance) should be divided by the number of paralleled caps that are used, especially if their leads share as little conductor length as possible (except don't incur too much extra lead or conductor length trying to achieve that).
And if the smaller caps have a smaller LS (lead spacing), then they should start out with lower inductance (than the larger original cap) and the benefit should be even greater.
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This method could be right just to reduce ESL, not the ESR
The smaller (physically) the cap, the higher the ESR, so paralleling more smaller caps doesn't give any real advantage about ESR
But it does about ESL, because while the ESR is inversely proportional to cap dimension, the ESL is directly proportional
The smaller (physically) the cap, the higher the ESR, so paralleling more smaller caps doesn't give any real advantage about ESR
But it does about ESL, because while the ESR is inversely proportional to cap dimension, the ESL is directly proportional
I have to agree. The ESL is much more important here. And I was trying to emphasize the ESL, originally. But I threw in the ESR at the last minute. I did try to hedge a little about the ESR, because there are two competing effects, making it unclear (to me, at the time) whether or not there would always be a beneficial effect on the ESR. Basicaly, I just didn't stop to think about it for quite long enough, before adding the ESR to my statements. I wish I had just left it out since it's a less-important parameter, here, anyway, and is now sort-of clouding the issue. But thanks for pointing out the error.
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