Finally got my shiny Si590 XOs today.
I now have my BuffaloIIIse playing from 16/44.1 to 24/384 and DSD128 with DPLL OFF
This is unreal! was expecting nothing better than lowest DPLL with this setup
Hey all,
I'm having some issues that might or might not be related to the S01 re-clocker board. I've written up in detail in another thread related to the Curryman 9023 DAC board and I'll post the information given there here because it might be relevant to my issue...
I've finally completed building my Curryman 9023! As usual, I'm running into a major issue with muffled and distorted audio and I'm not really sure where to start troubleshooting beyond initial power voltage readings. I'll detail how I have my configuration set up so things are easier to understand...
I'm using 3 power supplies all designed by AMB audio. The model of the supply is the Sigma 25. The first power supply is providing 5v to the DAC board and to an Acko S01 Isolator / Re-clocker board. The supply is connected to a terminal strip which then connects to the two separate boards. I'm reading +5v in to both boards and 3.3v or 3.6v after their respective LDO regulators (DAC, XO, and power for re-clocker board). The other two supplies are connected together to provide +/- 15v for the JG Buffer. I'm getting a reading of +/- 15v for this supply. So it looks like my power is in order.
In my particular configuration I decided to go with a pre-buffer / post-buffer switch. I'm using a DPDT switch that is only taking in the left and right channels of audio. No ground connections. Then my ground connections (all 4) are hooked directly up to my RCA terminals. So I'm not switching GND. Just L/R. This way I only need one set of RCAs.
I'm getting the noise, distortion pre and post buffer so the issue seems to be before the buffer.
The way I set up the XO and re-clocking is this way. I have the XO on board which feeds the re-clocker RCK and then the SDATA, LRCK, and BCK are feeding back into the DAC. So the on-board Clock is acting as reference for the re-clocker.
There are only two things that come to mind to be the issue... either the DAC chip or something is wrong with the re-clocker board.
Any ideas are appreciated.
~Mull3t
I'm having some issues that might or might not be related to the S01 re-clocker board. I've written up in detail in another thread related to the Curryman 9023 DAC board and I'll post the information given there here because it might be relevant to my issue...
I've finally completed building my Curryman 9023! As usual, I'm running into a major issue with muffled and distorted audio and I'm not really sure where to start troubleshooting beyond initial power voltage readings. I'll detail how I have my configuration set up so things are easier to understand...
I'm using 3 power supplies all designed by AMB audio. The model of the supply is the Sigma 25. The first power supply is providing 5v to the DAC board and to an Acko S01 Isolator / Re-clocker board. The supply is connected to a terminal strip which then connects to the two separate boards. I'm reading +5v in to both boards and 3.3v or 3.6v after their respective LDO regulators (DAC, XO, and power for re-clocker board). The other two supplies are connected together to provide +/- 15v for the JG Buffer. I'm getting a reading of +/- 15v for this supply. So it looks like my power is in order.
In my particular configuration I decided to go with a pre-buffer / post-buffer switch. I'm using a DPDT switch that is only taking in the left and right channels of audio. No ground connections. Then my ground connections (all 4) are hooked directly up to my RCA terminals. So I'm not switching GND. Just L/R. This way I only need one set of RCAs.
I'm getting the noise, distortion pre and post buffer so the issue seems to be before the buffer.
The way I set up the XO and re-clocking is this way. I have the XO on board which feeds the re-clocker RCK and then the SDATA, LRCK, and BCK are feeding back into the DAC. So the on-board Clock is acting as reference for the re-clocker.
There are only two things that come to mind to be the issue... either the DAC chip or something is wrong with the re-clocker board.
Any ideas are appreciated.
~Mull3t
Finaly, after 2 months I've found some spare time to put S03 board in the DAC box. I was discouraged at the begining of test then I realised that I didn't set amanero to slave mod
. Now on LST settings there is no unlocks but I only tested it with 44 khz - it's realy late now. On regular Buffalo III that was impossible (in async mode with Crystek 100MHz). Anybody knows how to implement corect frequency display in arduino software?
. Now on LST settings there is no unlocks but I only tested it with 44 khz - it's realy late now. On regular Buffalo III that was impossible (in async mode with Crystek 100MHz). Anybody knows how to implement corect frequency display in arduino software?
Finaly, after 2 months I've found some spare time to put S03 board in the DAC box. I was discouraged at the begining of test then I realised that I didn't set amanero to slave mod
This is great progress!
When you get the chance please try No DPLL BW and see if it still locks
How to set No DPLL BW? In arduino controller software LST is the lowest setting.
In that case you will need to poke the registers directly. Is there a write register cmd?
I'm using firmware from ce-design so yes, there is a write register cmd. I just need to know values and registers.
Also displayed sample rate is constantly changing.
BW Registers
Register #11 controls the DPLL BW
bits 2-4 sets the BW values, shown LST:
b7=1
b6=0
b5=0
b4=0
b3=0
b2=1
b1=0
b0=1
for No BW set as follows:
b7=1
b6=0
b5=0
b4=0
b3=0
b2=0
b1=0
b0=1
The Hex value for the above is 81 or Decimal:129
Write this value into Register #11 and DPLL will turn off
0 (F3), 0 (F2), 0(F1), 0(F0) -> 32kHz
0 (F3), 0 (F2), 0(F1), 1(F0) -> 44.1kHz
0 (F3), 0 (F2), 1(F1), 0(F0) -> 48kHz
0 (F3), 0 (F2), 1(F1), 1(F0) -> 88.2kHz
0 (F3), 1 (F2), 0(F1), 0(F0) -> 96kHz
0 (F3), 1 (F2), 0(F1), 1(F0) -> 176.4kHz
0 (F3), 1 (F2), 1(F1), 0(F0) -> 192kHz
0 (F3), 1 (F2), 1(F1), 1(F0) -> 352.8kHz
1 (F3), 0 (F2), 0(F1), 0(F0) -> 384kHz
Note: on the green Amanero these F0-F3 lines are actually grounded. Not sure removing gnd connections of the corresponding pins (17-20) of Amanero will make it equivalent to the red edition?
Register #11 controls the DPLL BW
bits 2-4 sets the BW values, shown LST:
b7=1
b6=0
b5=0
b4=0
b3=0
b2=1
b1=0
b0=1
for No BW set as follows:
b7=1
b6=0
b5=0
b4=0
b3=0
b2=0
b1=0
b0=1
The Hex value for the above is 81 or Decimal:129
Write this value into Register #11 and DPLL will turn off
This is a known issue and has also been reported elsewhere, i.e. when in sync mode the DAC cannot resolve the samples rates. I am not sure if anyone else has found a workaround. Until then it is best to get this directly from the transport. The new version of Amanero (red board) reports sample rates on the lines F0, F1, F2 and F3. So if controller supports I/O then read these lines accordingly:
0 (F3), 0 (F2), 0(F1), 0(F0) -> 32kHz
0 (F3), 0 (F2), 0(F1), 1(F0) -> 44.1kHz
0 (F3), 0 (F2), 1(F1), 0(F0) -> 48kHz
0 (F3), 0 (F2), 1(F1), 1(F0) -> 88.2kHz
0 (F3), 1 (F2), 0(F1), 0(F0) -> 96kHz
0 (F3), 1 (F2), 0(F1), 1(F0) -> 176.4kHz
0 (F3), 1 (F2), 1(F1), 0(F0) -> 192kHz
0 (F3), 1 (F2), 1(F1), 1(F0) -> 352.8kHz
1 (F3), 0 (F2), 0(F1), 0(F0) -> 384kHz
Note: on the green Amanero these F0-F3 lines are actually grounded. Not sure removing gnd connections of the corresponding pins (17-20) of Amanero will make it equivalent to the red edition?
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I've just change the code but I'm not sure about register 10 and jitter reduction enable bit. Sometimes when DPLL(on reg 11) is off if I disable jitter reduction(on reg 10) it can't get the lock and when I go thru the menu selection (NOR, MUL and OFF) it locks sometimes on OFF and doesn't lose the lock. It always locks on NOR(x1). On jitter enable OFF it's very inconsistent, simetimes it gets the lock sometimes don't.
I have the old version of amanero board and I know it's possible to get the F0-F3 lines directly from IC pins but ... these pins are so close
to each other.I think it is best you set Reg10 with Jitter Reduction ON. We are just testing DPLL BW on Reg#11
SO3 questions
Hi. I have a few S03 board questions, probably already answered (or too simple to have been asked):
1) R14-R17 should be same as R9-R12?
2) The u.fl digital inputs are to be able to use the board with other devices besides Amanero's?
3) Do we need to install C1?
4) Has anybody used a LiFePO battery to power the clock (like Ian's FIFO clock, can use his charger to keep it charged)? If so:
Hi. I have a few S03 board questions, probably already answered (or too simple to have been asked):
1) R14-R17 should be same as R9-R12?
2) The u.fl digital inputs are to be able to use the board with other devices besides Amanero's?
3) Do we need to install C1?
4) Has anybody used a LiFePO battery to power the clock (like Ian's FIFO clock, can use his charger to keep it charged)? If so:
a) feed the battery into J2
b) what is C9 in this case?
c) don't connect any of the Kx jumpers? If I did choose say option #2 for power and decided to test the battery for the clock, can I just add C9, unsolder the K2 jumper and leave the option #2 reg/caps there?
d) no pins were used to select LDO (the Kx solder pads for jumper wire instead) to minimize the antenna effect the pins might provide?
Thanks in advance.b) what is C9 in this case?
c) don't connect any of the Kx jumpers? If I did choose say option #2 for power and decided to test the battery for the clock, can I just add C9, unsolder the K2 jumper and leave the option #2 reg/caps there?
d) no pins were used to select LDO (the Kx solder pads for jumper wire instead) to minimize the antenna effect the pins might provide?
can be the same
this can be done. If transports allow external clock then you get the same benefits of Full Sync Re-Clocking as the Amanero. Otherwise simple re-clocking.
Yes, if you are using the on-board LDOs for XO
Interesting to see the benefits of battery or shunt regs for this design. K1, K2 and K3, all must be disconnected if external power is used. Associated Regs/Caps can remain on board. C9 - 10u-100uf. Link pads instead of headers were used to squeeze in everything. possibly some benefits like short low res connection close to tracks
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