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Amanero Isolator/Reclocker GB

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K

KlipschKid

Banned
Joined 2007
Acko - how about filling the uinused vias with solder - what dya think ?

For mkii, it'd be cool to add routing + pads for a 5x7 xo for rclk, and routing + pads for adp151 on the input side to allow 5v input. This'd make it more suitable for a wide range of DACs.

I'll be hoping to find time to test this next week - got 3 different isos - adum3440, iso7240 and NVE 715 to try, and 3 different xo's - 100 and 125 fox and 150 saw. Just too busy these days.

Anyone got theirs up and running yet ?
 
A

acko

Member
Joined 2008
sites.google.com/site/ackodac/home
KlipschKid said:
Acko - how about filling the uinused vias with solder - what dya think ?
Click to expand...
The layout is such that the currents circulate mainly on the top gnd plane (as the IC pins) and returns to power gnd on the top side. The bottom ground plane acts more like a shield, stitched with vias to the top gnd plane-all for HF performance. So I am not sure if you would get any further benefits in solder linking the vias but no harm doing so.


KlipschKid said:
For mkii, it'd be cool to add routing + pads for a 5x7 xo for rclk, and routing + pads for adp151 on the input side to allow 5v input. This'd make it more suitable for a wide range of DACs.
Click to expand...

Will consider... added to wishlist:)
 
A

acko

Member
Joined 2008
sites.google.com/site/ackodac/home
acko said:
Yes, RCK is the reference clock for the flip-flop. The quality of the regenerated output signals depend on this clock and also how cleanly the flip-flops switch. If you skimp on these the overall SQ may not be up to expectations.

RCK can be from a separate clock or tied to DAC MCLK. When used separately RCK is async w.r.t to the audio signals (I2S/DSD) and actually modulates the pulse width of the signals if you look at the timing/switching carefully. To minimize the effects RCK should be running higher that the max Fs, higher the better accuracy of the outputs. e.g. for 24.576MHz of typical transport clock, we are looking at ~50MHz minimum. 100MHz even better. Of course you could go higher if the Flip-flops can take it. The S01 ~200Mhz max but the PotatoChip version (S02) can be fried up to 600MHz! If also appears that XOs have better stability and lower phase noise at higher freqs and also there are some discussions on this SAW technology being better? ..
Click to expand...


More App Notes ...
 

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  • App Notes - Sync Mode.pdf
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  • App Notes - PSync Mode.pdf
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K

KlipschKid

Banned
Joined 2007
Hi Acko,

Got the "slow" board up and running today - using adum3440, 125Mhz Fox on rclk, and SN74AUP1G79DBVR as flipflops. Source is a cm6631A (45/49 mhz clocks), 192Khz @32bit into AKM AK4399 DAC (no local clock - uses isolated/re-clocked mclk from cm6631a). It sounds very good even in the temporary hook-up condition. Thank you for doing this project !

Cheers,

Tom
 
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A

acko

Member
Joined 2008
sites.google.com/site/ackodac/home
hochopeper said:
At least initially I will be using iancanada's Si570 @98MHz for RCLK, because I have no other clocks fast enough at hand (seems a bit ridiculous but hey we're all having fun!)
Click to expand...


Realised that many others may not have any clock modules to play with (for RCK). Whilst you can tap into DAC XO to share if there exist one but will not cover all options as indicated in the App Notes.
Could take a bit of effort to build one on your own from scratch especially smd ones that require pcb to start with. I am not sure if anyone else has done something like this (apart from Ian) that so I will roll out a simple Clock board to make it easier.
You can then assemble it with XO and components of choice. XO will have 5X7mm footprint and there are several options from Crystek, Fox, MEC, Epson etc, and you can go all the way up to 500MHz for the SO2 board. More details will be provided later.

Hope this helps
 
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H

hochopeper

Member
Joined 2009
Acko, I think most people's DAC XO is not going to be fast enough either. Also most DAC XO's are probably not going to drive a (relatively) long connection very well.

I was thinking about something similar to what you've suggested, probably with Demian's low power series regulator and an XO and maybe an optional buffer IC, could be quite a compact but high performance package there I'd expect.

Though for simplicity I may just use one of Ian's XO adapter PCBs that I have spare along with a separate reg. I've certainly got options but none of them are as plug and play as Ian's Si570 (though I still need to assemble a tps7a regulator to power my si570 yet).

There is a few options already but they require a bit extra DIY effort and your solution would certainly be the most convenient. The same board could also be used for people with AKD23P or AKD16 to compare async mclk to sync for the ES9023 and ES9016 regardless of if they are using the reclocker :)
 
M

MisterRogers

Member
Joined 2011
Thanks Acko - such a clock board would be most welcome! I had the same thought Chris did while mulling it in the shower yesterday (sorry - too much info :); to use one of my si570's for now. Overkill for your 9023 board, but it'll get me going.

So I put together an SO2 (fully built), grabbed the si570 and wired it up to a BIIISE for testing. For the most part, it seems to be working in async, sync and psync modes. Certain frequencies seem to struggle to find the 'edge' of the signal, but when they did they'd lock. I suspect it's the inverted MCLK that the si570 is configured for by default. Could that be causing this when used as RCLK?
 
H

hochopeper

Member
Joined 2009
MisterRogers said:
Thanks Acko - such a clock board would be most welcome! I had the same thought Chris did while mulling it in the shower yesterday (sorry - too much info :); to use one of my si570's for now. Overkill for your 9023 board, but it'll get me going.

So I put together an SO2 (fully built), grabbed the si570 and wired it up to a BIIISE for testing. For the most part, it seems to be working in async, sync and psync modes. Certain frequencies seem to struggle to find the 'edge' of the signal, but when they did they'd lock. I suspect it's the inverted MCLK that the si570 is configured for by default. Could that be causing this when used as RCLK?
Click to expand...

I could be wrong but I cannot see Si570 inverted MCLK being an issue in anything other than PSYNC, even then, it is questionable if MCLK relative to the other signals is important. If you are using MCLK as the input MCLK to a BIII SE then an inverted MCLK is more likely to be an improvement given ESS's previous advise on these matters.

Chris
 
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