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Old 29th March 2013, 07:24 AM   #511
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How'd I miss that??

Quick searching effort returns this - Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

I will add that to the FIFO wiki too for future reference.
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Old 29th March 2013, 07:29 AM   #512
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For future reference of spectators, my post was before your edit :P
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Old 29th March 2013, 07:55 AM   #513
qusp is offline qusp  Australia
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LMFAO

also to be clear, in addition to the 2ps noise floor, these measures are at the actual output of the clock buffer, not of the si570 itself, so the small jitter added by the potato FF is included. also note the cool speed i'd say the board would need a bit of software hacking to enable higher than 98.304MHz, but its most certainly capable of it
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Old 29th March 2013, 08:59 AM   #514
acko is offline acko  Australia
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Thank Guys, helps a lot! I started to spin of this Clock module because of the 100Mhz limit of Ian module and the re-clocker can take higher speeds. Anyway it is all good to experiment. I will check out Ian's design. Trying to avoid duplication and wasting time... My own DACs have no XO on-board so welcome anything favourable.

Chris, you are right. Confusion with the term Sync can creep in quickly and can be a fine line at times. e.g. if RCK is clocked at 98.304Mhz or 196.608MHz instead (and linked to DAC MCK) then it becomes in "True" sync with some of the higher Sampling Frequencies. So "Pseudo" Sync at other RCK frequencies even if DAC MCK is linked to RCK. Hope this clarifies
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Last edited by acko; 29th March 2013 at 09:08 AM.
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Old 29th March 2013, 10:21 AM   #515
acko is offline acko  Australia
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Quote:
Originally Posted by qusp View Post
....
dividing a higher speed clock to get the dac clock will reduce the period jitter of the signal itself, but it will add a small amount from the additional flip flop, I feel pretty sure that this would outweigh any reduction from the division.
.....

Quote:
Originally Posted by qusp View Post
... in addition to the 2ps noise floor, these measures are at the actual output of the clock buffer, not of the si570 itself, so the small jitter added by the potato FF is included.
...
I see from Ian's results the additive jitter from the FFs themselves are minimal
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Old 29th March 2013, 11:19 AM   #516
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sure I know, I didnt mean it was significant overall, but its very likely more significant than the reduction by dividing and dividing will only reduce period jitter I would think, not phase jitter. the impact of the FF will depend on which FF and the interconnection/load line I would think. I wonder if we can expect the same performance from a division circuit vs a straight buffer. interesting questions that can only really be answered by measuring

It also relies on you being able to find a 200MHz clock that is lower jitter (close in jitter) than the 50-100MHz clocks that are fairly readily available, i'm not aware of any, the si570 itself will do much more than that though.

Last edited by qusp; 29th March 2013 at 11:22 AM.
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Old 29th March 2013, 11:28 AM   #517
acko is offline acko  Australia
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Quote:
Originally Posted by qusp View Post
...
It also relies on you being able to find a 200MHz clock that is lower jitter (close in jitter) than the 50-100MHz clocks that are fairly readily available,
...
Yes, of course, boils down to intrinsic phase jitter of the XOs mainly
Thanks!
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Old 30th March 2013, 08:22 AM   #518
qusp is offline qusp  Australia
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let the fun begin! i've mostly finished building up the Ti side, will try it out tomorrow
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Old 30th March 2013, 10:08 AM   #519
acko is offline acko  Australia
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Quote:
Originally Posted by acko View Post
....
e.g. if RCK is clocked at 98.304Mhz or 196.608MHz instead (and linked to DAC MCK) then it becomes in "True" sync with some of the higher Sampling Frequencies. So "Pseudo" Sync at other RCK frequencies even if DAC MCK is linked to RCK.
....
Correction and apologies! For the AKL-AMN board simply applying 98.304MHz at RCK does not turn it into "True" Sync mode as indicated earlier as the Bit clock from transport is not exactly in sync with RCK. So still PSync.

True Sync mode is only as shown in the App Notes for "Sync Mode" but limited to Fs up to 192KHz due the Amanero Clock limitation at 24.576MHz. Appears that there is a double clock version of Amanero (49.152MHz) available and this should able to take higher Fs

High Fs True sync operation can also be realised if the clock module interacts with the transport such as the AKX701 Turbo Clock and of course Ian's Si570 Clock Module
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Old 30th March 2013, 12:41 PM   #520
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Quote:
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LMFAO

also to be clear, in addition to the 2ps noise floor, these measures are at the actual output of the clock buffer, not of the si570 itself, so the small jitter added by the potato FF is included. also note the cool speed i'd say the board would need a bit of software hacking to enable higher than 98.304MHz, but its most certainly capable of it
I just had a peak at my Si570 board .. there are NXP FF on the final production boards.
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