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Old 28th March 2013, 04:16 PM   #501
qusp is offline qusp  Australia
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Quote:
Originally Posted by acko View Post
Prefer clock division to drive DAC MCLK. e.g if RCK is 200MHz then use a /2 to 100MHz clock for DAC.
sure theoretically, but...

that depends, i'm not aware of any readily available 200MHz XOs that are better (particularly for close in phase noise) than the clocks available in the lower range and multiplication is a pretty simple job with parts available that are very low jitter. its my feeling that its best to have the highest quality clock on the dac, dividing a higher speed clock to get the dac clock will reduce the period jitter of the signal itself, but it will add a small amount from the additional flip flop, I feel pretty sure that this would outweigh any reduction from the division.

I dont believe RCK is more important than MCK... MCK will have the last say with ESS and i'm not convinced the higher speed the better for RCK due to added demands on the PCB and supply. so compromising the dac MCK in order to gain a theoretical improvement from RCK earlier in the chain seems odd to me.

for instance the si570 could probably have its second clock buffer changed for a x2 for RCK, or it could I suppose be set to the higher speed natively for RCK and change one of the buffers to a div/2 for MCK, no additional part on either scheme

Last edited by qusp; 28th March 2013 at 04:21 PM.
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Old 28th March 2013, 05:11 PM   #502
LuisMCP is offline LuisMCP  Spain
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Quote:
Originally Posted by hochopeper View Post
Just solder wires to the pads? the small centre-top u.fl pad is the signal, the other two are ground.
ouch! too small for me.

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Originally Posted by acko View Post
Or, if you do not wish to solder wires on the pads just mount U.FL connectors. Then get suitable U.FL lead assembly and on the other ends cut off the 'heads', extract the wires and dovetail connections to the DAC pin headers. Keep lengths as short as possible.
mmm... what a pitty cutting these "cool" cables.
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Old 28th March 2013, 06:12 PM   #503
qusp is offline qusp  Australia
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alternatively you could spin a PCB to adapt the pin-header on the dac to u.fl
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Old 28th March 2013, 08:56 PM   #504
acko is offline acko  Australia
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Quote:
Originally Posted by qusp View Post
sure theoretically, but...

that depends, i'm not aware of any readily available 200MHz XOs that are better (particularly for close in phase noise) than the clocks available in the lower range and multiplication is a pretty simple job with parts available that are very low jitter. its my feeling that its best to have the highest quality clock on the dac, dividing a higher speed clock to get the dac clock will reduce the period jitter of the signal itself, but it will add a small amount from the additional flip flop, I feel pretty sure that this would outweigh any reduction from the division.

I dont believe RCK is more important than MCK... MCK will have the last say with ESS and i'm not convinced the higher speed the better for RCK due to added demands on the PCB and supply. so compromising the dac MCK in order to gain a theoretical improvement from RCK earlier in the chain seems odd to me.

for instance the si570 could probably have its second clock buffer changed for a x2 for RCK, or it could I suppose be set to the higher speed natively for RCK and change one of the buffers to a div/2 for MCK, no additional part on either scheme
Thanks Qusp, points noted but no harm trying.

I have updated the Clock board with div/2 and div/4 output options for MCK and in snyc with RCK.
You could something similar with si570 but how do you sync them?
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Last edited by acko; 28th March 2013 at 09:06 PM.
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Old 28th March 2013, 09:09 PM   #505
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Also worth noting that you can still use MCLK from the Amanero without using the clock division on the MCLK.

For a 200MHz RCLK clock I don't think we've really stressed this PCB or the parts too much.
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Old 29th March 2013, 04:58 AM   #506
qusp is offline qusp  Australia
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Originally Posted by acko View Post
Thanks Qusp, points noted but no harm trying.

no of course not, try what you like, thats the point of tyhese little boards, it just doesnt make sense to me to prioritize RCK jitter over MCK and I think thats what the setup above does.

Quote:
I have updated the Clock board with div/2 and div/4 output options for MCK and in snyc with RCK.
You could something similar with si570 but how do you sync them?
sync what to what? the si570 module has 2 buffered outputs to cater for dual mono, if you divide one and steal the reference clock from the higher speed output, wouldnt both be in sync?


Quote:
Originally Posted by hochopeper
For a 200MHz RCLK clock I don't think we've really stressed this PCB or the parts too much.
too much? no, more? yes and total noise RMS will of course be higher with higher speed.
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Old 29th March 2013, 05:44 AM   #507
acko is offline acko  Australia
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Originally Posted by qusp View Post
... the si570 module has 2 buffered outputs to cater for dual mono, if you divide one and steal the reference clock from the higher speed output, wouldnt both be in sync?
Ok thanks got it. From the same output, of course.

But
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Originally Posted by qusp View Post
..... div/2 for MCK, no additional part on either scheme
you will need additional parts like FFs

This is what my own clock module is doing. However, I am not really warming to the idea of Si570 with its PLL synthesized output being any better than a native cut XO. Has any one tried Si570 with ESS DAC (for MCK) and compared results e.g with CCHD950 or similar?
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Last edited by acko; 29th March 2013 at 05:59 AM.
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Old 29th March 2013, 05:59 AM   #508
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To save confusion, is there a better word than synch that we can use when the MCLK is in synch with all signals, but also a direct multiple of the sample rate? I can see that some would easily get confused between the two different modes that we're using the same word for. I think this is why you used the psynch term in your docs Acko, I can see already there is some mixing up of the terms here, though the use of synch in the recent posts is all technically correct, if read by people who're on the ball. I am, however, worried a touch that some in this thread aren't all at the same level of understanding and the mix and match vocab perhaps doesn't make it easy.



Acko, Ian developed an Si570 board and tested it, he prefers it I've put together a wiki page compiling links to different parts of Ian's projects - his posts on his Si570 experiments are all here - Ian's I2S FIFO Project - diyAudio - his comment was that he preferred the final revision of the Si570 using the TPS7A4700 regulator that I linked - when the Si570 is operating at 95/98Mhz. He previously used his DualXO board with CCHD957 @ 45/49MHz clocks. He posted some measurements too, from memory both arrangements are below the noise floor of his equipment.

Last edited by hochopeper; 29th March 2013 at 06:04 AM.
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Old 29th March 2013, 06:14 AM   #509
qusp is offline qusp  Australia
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Quote:
Originally Posted by acko View Post
Thanks Qusp, points noted but no harm trying.

I have updated the Clock board with div/2 and div/4 output options for MCK and in snyc with RCK.
You could something similar with si570 but how do you sync them?
Quote:
Originally Posted by acko View Post
Ok thanks got it. From the same output, of course.

But

you will need additional parts like FFs

This is what my own clock module is doing. However, I am not really warming to the idea of Si570 with its PLL synthesized output being any better than a native cut XO. Has any one tried Si570 with ESS DAC (for MCK) and compared results e.g with CCHD950 or similar?
I was suggesting that you could replace one of the buffer positions on the board, not nessecarily add one, but even if it meant adding one I think adding some small amount of jitter to RCK vs MCK is not a big deal anyway, since MCK will have the final say.

the si570 uses a pure crystal at its heart. check Ians measurements out, they are very impressive, not quite as good as crystek, but still VERY low, insignificantly low given the flexibility it gives. I dare say lower than any of the 200MHz clocks youve mentioned. actually from memory it was objectively better than chhd950, but not as good as 957. theoretically anyway, because as chris mentions, its performance is buried below Ians 2ps measurement noise floor, but the output is VERY clean

Last edited by qusp; 29th March 2013 at 06:18 AM.
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Old 29th March 2013, 06:19 AM   #510
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on that note Chris, I noticed you dont have the si570 measurements linked in the wiki

here they are

Last edited by qusp; 29th March 2013 at 06:26 AM.
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