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Old 26th March 2013, 05:30 AM   #491
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Quote:
Originally Posted by MisterRogers View Post
Nope, not for MCLK of the 9018.
Cool, I just wanted to be sure that no-one else misconstrues recommendations for fast RCLK as a recommendation for exceeding the DAC chips max MCLK spec.

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Originally Posted by MisterRogers View Post
Yea, I've picked up on your preference for faster clocks; sounds intriguing to me and makes alot of sense. That Fox is exactly the sort of recommendation I was looking for. Keep them coming :-)
Since Acko's designed a board that lets us use parts that go fast, it is mighty tempting to go as fast as possible. I just haven't found a faster clock yet at reasonable prices/availability that looks well speced for the job. For $5-10 ea those Fox ones seem pretty decent. The usual suspects didn't appear to be available upwards of 100MHz though when I went looking the other day, if I find others I'll report back here.

I might actually probably grab a 50MHz and a 200MHz of the same clock and see what there is to see, I'm not expecting a huge difference, though as you say, for faster sample rates, the slower clock isn't going to get the job done.

I keep meaning draw up some timing diagrams at some point to help me better visualise the signals being reclocked by the faster RCLK. I haven't had time to do that yet though.

One day I hope to have an ADC that is good enough that it might help me make these decisions.
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Old 26th March 2013, 02:30 PM   #492
qusp is offline qusp  Australia
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why not just multiply the dac clock?
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Old 26th March 2013, 02:41 PM   #493
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Originally Posted by qusp View Post
why not just multiply the dac clock?
Doesn't make sense to reclock with a synthetic clock does it? RCLK jitter is crucial to reclock performance since it is the CLK input on the flip flops.
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Old 26th March 2013, 03:22 PM   #494
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My board arrived, thank you.
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Old 26th March 2013, 06:17 PM   #495
acko is offline acko  Australia
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Quote:
Originally Posted by qusp View Post
why not just multiply the dac clock?
Quote:
Originally Posted by hochopeper View Post
Doesn't make sense to reclock with a synthetic clock does it? RCLK jitter is crucial to reclock performance since it is the CLK input on the flip flops.
Prefer clock division to drive DAC MCLK. e.g if RCK is 200MHz then use a /2 to 100MHz clock for DAC.
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Old 27th March 2013, 10:21 AM   #496
LuisMCP is offline LuisMCP  Spain
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Default UFL connectors

My DAC don't has any UFL connector as input.

How to connect these UFL connectors to my DAC?
It has only common pin head 2,54 mm connectors.

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Old 28th March 2013, 02:20 AM   #497
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Just solder wires to the pads? the small centre-top u.fl pad is the signal, the other two are ground.
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Old 28th March 2013, 05:46 AM   #498
acko is offline acko  Australia
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Or, if you do not wish to solder wires on the pads just mount U.FL connectors. Then get suitable U.FL lead assembly and on the other ends cut off the 'heads', extract the wires and dovetail connections to the DAC pin headers. Keep lengths as short as possible.
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Old 28th March 2013, 06:05 AM   #499
acko is offline acko  Australia
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Quote:
Originally Posted by qusp View Post
why not just multiply the dac clock?
Quote:
Originally Posted by hochopeper View Post
Doesn't make sense to reclock with a synthetic clock does it? RCLK jitter is crucial to reclock performance since it is the CLK input on the flip flops.
Quote:
Originally Posted by acko View Post
Prefer clock division to drive DAC MCLK. e.g if RCK is 200MHz then use a /2 to 100MHz clock for DAC.
Something like this... RCK spinning higher means we can take advantage of better stability and jitter performance of XOs. If Pulse Modulation Error is a concern as what GLT indicated then this is minimized with the higher RCK frequency. Also, I am assuming jitter is Freq domain stuff and dividing to get MCK means jitter is reduced?
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Last edited by acko; 28th March 2013 at 06:27 AM.
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Old 28th March 2013, 06:35 AM   #500
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Quote:
Originally Posted by acko View Post
Something like this... RCK spinning higher mean we can take advantage of better stability and jitter performance of XOs. If Pulse Modulation Error is a concern as what GLT indicated then this is minimized with the higher RCK frequency. Also, I am assuming jitter is Freq domain stuff and dividing it to get MCK means jitter is reduced?
Thanks for this Acko, I follow the logic, seems like a good idea and I'll probably give it a go! I'll see if I can draw some diagrams of the signals in different configurations to improve my understanding, will report here if I find anything interesting.


Looks like a good level of interest in the AKX301 in the spreadsheet too

Any of the other Australian's got their PotatoChips yet? How long did your chips take to get here from PotSemi?

Last edited by hochopeper; 28th March 2013 at 06:37 AM.
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