Whilst waiting for my Si590 oscillators to arrive I lashed up a Fox Expresso FVXO-HC73B-98.3040 with a passive distribution board.
I now have the Amanero and BuffaloIIIse running full sync via acko's Isolator/Reclocker with the Expresso at 98.3040Mhz providing MCK.
Amazing considering the torturous route the MCK takes.
I now have the Amanero and BuffaloIIIse running full sync via acko's Isolator/Reclocker with the Expresso at 98.3040Mhz providing MCK.
Amazing considering the torturous route the MCK takes.
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Out of interest, is there any advantage to using the amanero dividers versus the potsemi divider (apart from cost saving)?
Whilst waiting for my Si590 oscillators to arrive I lashed up a Fox Expresso FVXO-HC73B-98.3040 with a passive distribution board.
I now have the Amanero and BuffaloIIIse running full sync via acko's Isolator/Reclocker with the Expresso at 98.3040Mhz providing MCK.
Amazing considering the torturous route the MCK takes
Fantastic
Just to clarify, you could not get this to work with Ian's Si570 clock but doing the above sorted out matters. So Amanero FW is fine then. Any ideas why the former did not work? I cannot see why the Si570 setup failed for 98.304. What was the Fs used at 98.304MHz?
There are a few things to consider:
1. Cost saving plus one less switching component on board.
2 The full XO frequency goes into the isolator chip (IL712) if Postemi divider bypassed. e.g. 98Mhz going into IL712 instead of the divided 49.xx or 24.xxMhz
3. Potsemi FF on the board also buffers the XO output. If bypassed then the IL712 loads the XO with its input capacitance-this value is not specified for Il712. Could have some effects.
Anyway, we need to experiment further to confirm.
Fantastic
Just to clarify, you could not get this to work with Ian's Si570 clock but doing the above sorted out matters. So Amanero FW is fine then. Any ideas why the former did not work? I cannot see why the Si570 setup failed for 98.304. What was the Fs used at 98.304MHz?
With Ian's Si570 clock I could not get 90/98 to work.
Ian's Si570 works fine for all MCK with Ian's FIFO.
Ian's Si570 looks OK on 'scope (Definition of OK, uncalibrated 1982 100Mhz 'scope). Strange its not working with Amanero.
The Fox Expresso sorted out 98.304MHz MKC for ALL Fs up to 384k.
Amanero firmware is fine. Including Pin 1 (Clock Select) toggles correctly when the Fs group changes.
Pin 11 (Mute) pulses high (not sure how wide the pulse is) when Fs group changes.
I think I already tried this but, Going to try all Fs With Ian's Si570 clock @ 90/98.
if we remember, running reclocked sync mode with the onboard clocks on amanero driving the flip flop resulted in silence, even though here we are not using the onboard clocks, we may as well be, the result is the same.
so I dont have to explain it, see here for details on hifiduino last year. I mentioned this much earlier in this thread, before the boards were made. so Acko, its not your error, just an incompatibility I think.
that being said, deanoUK, the si570 has the ability to invert MCK, you may be able to invert mck for 352.8/384khz and leave it as is for 176.4/192 (inverting MCK will result in the latter not working, rather than the former. given the number of available opportunities for changing things either on the reclock board or asking nicely for amanero to have a function to fix this, I think we can sort it out without any actual hardware changes.
any ideas guys?
so I dont have to explain it, see here for details on hifiduino last year. I mentioned this much earlier in this thread, before the boards were made. so Acko, its not your error, just an incompatibility I think.
that being said, deanoUK, the si570 has the ability to invert MCK, you may be able to invert mck for 352.8/384khz and leave it as is for 176.4/192 (inverting MCK will result in the latter not working, rather than the former. given the number of available opportunities for changing things either on the reclock board or asking nicely for amanero to have a function to fix this, I think we can sort it out without any actual hardware changes.
any ideas guys?
Fantastic
Just to clarify, you could not get this to work with Ian's Si570 clock but doing the above sorted out matters. So Amanero FW is fine then. Any ideas why the former did not work? I cannot see why the Si570 setup failed for 98.304. What was the Fs used at 98.304MHz?
Got it working @ 90/98.
This is what makes it work, or at least a longer cable from the Si570 to the BuffaloIIIse.The route for Si570 MCK through the acko AKL-AMN-S03 is longer than the route for Si570 MCK->BuffaloIIIse.
So a longer cable Si570->BuffaloIIIse compensates for the delay.
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interesting, which divider on amanero are you using? actually now I remember, Ian changed the si570 to have inverted MCK as the default setting late in development. I have one here, but havent played with it as yet.
the above is a real problem but will depend on the reclocking and MCK settings (rising/falling edge, normal or inverted mclk) perhaps just having faster mclk going to the ESS is enough despite these problems even if its still synchronous.
regardless, glad you sorted it out.
the above is a real problem but will depend on the reclocking and MCK settings (rising/falling edge, normal or inverted mclk) perhaps just having faster mclk going to the ESS is enough despite these problems even if its still synchronous.
regardless, glad you sorted it out.
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I don't think this is the case. The re-clocking for S03 board is done by the much higher "destination" MCK (98/90M) w.r.t to BCK (22/24M max @384KHz Fs). See later part of Hifiduino's notes
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This is very interesting!
On the other hand keeping all clock paths as short as possible will also have similar effects. The S03 board does that internally with its own XOs mounted, so that leaves the 'Turbo MCK" to DAC MCK and Digital Input connections to be sorted out.
BTW, have you tried the lowest BW setting to see if DAC locks?
Many thanks
Locks but clicks and pops pretty much regardless of BW setting for DAC,
but I am not surprised considering the MCK lash up.
Using on board XO will no doubt yield a better result.
However , as MCK goes through the iL712 adding a propagation delay
of around 10nS and then LRCK/BCK/SDATA return through NVE715-3E
adding another 10nS of delay does this not mean they lag Turbo MCK by 20nS (around 2 ticks of MCK at 98.304MhZ) ?
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Ok, it is crunch time now
Let's see how it goes with the delays going through isolators. If needed we can match the delays by adjusting R1,R2,R3 or R4. Possibly a good idea to first link out R3 or R4 (div2/4) going into the IL712 so as not to add more delays here.
Ok, it is crunch time now
Let's see how it goes with the delays going through isolators. If needed we can match the delays by adjusting R1,R2,R3 or R4. Possibly a good idea to first link out R3 or R4 (div2/4) going into the IL712 so as not to add more delays here.
I am not using the on board clock divider circuitry.
With all due respect,
I am now thinking its a complete fluke it works at all.
The delay on LRCK/BCK/DATA must be near to an integral of MCK by sheer
luck (2*10.17ns).
Given that the delays through isolator, sample to sample, will vary, delays would need to be "tuned".
I hope I am wrong.
Wish I had a Logic Analyzer.
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I am not using the on board clock divider circuitry.
With all due respect,
I am now thinking its a complete fluke it works at all.
The delay on LRCK/BCK/DATA must be near to an integral of MCK by sheer
luck (2*10.17ns).
Given that the delays through isolator, sample to sample, will vary, delays would need to be "tuned".
I hope I am wrong.
Wish I had a Logic Analyzer.
Hmm..., let's do some comparisons. You have Ian's Si570 and FIFO.
Does this setup lock at 98M without clips and pops at the lowest BW?
The techniques appear similar. For Ian's design 98/90M Clock is isolated and goes into the FIFO and the I2S output from FIFO is isolated and then re-clocked by the same output 98/90M clock. FFs and Isolators are similar in both cases.
I agree on all points.
My analysis must be wrong.
So I am now thinking the main difference is that the clock gets sent back
to the FIFO, not the Amanero.
03:30 here, will have another think/look later.
by lowest deanoUK, are you actually meaning lowest, or No Bandwidth?
it could of course be those pesky 2.54mm headers simply not being up to the job and amanero grounding being a little bit less than optimal IMO
Ian does have the ability to adjust the delays on the lines individually with the FPGA and goes through many months of sims and board iterations before releasing something, giving time for revisions because hes a little bit obsessive
the si570 module for example, I lost count the number of board revisions he made before the first ones went into the wild. not at all economically viable.
it could of course be those pesky 2.54mm headers simply not being up to the job and amanero grounding being a little bit less than optimal IMO
Ian does have the ability to adjust the delays on the lines individually with the FPGA and goes through many months of sims and board iterations before releasing something, giving time for revisions because hes a little bit obsessive
the si570 module for example, I lost count the number of board revisions he made before the first ones went into the wild. not at all economically viable.
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by lowest deanoUK, are you actually meaning lowest, or No Bandwidth?
it could of course be those pesky 2.54mm headers simply not being up to the job and amanero grounding being a little bit less than optimal IMO
Ian does have the ability to adjust the delays on the lines individually with the FPGA and goes through many months of sims and board iterations before releasing something, giving time for revisions because hes a little bit obsessive
the si570 module for example, I lost count the number of board revisions he made before the first ones went into the wild. not at all economically viable.
"Ability to adjust the delays"
Do you know that he actually does this ?
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