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#1001 | ||
diyAudio Member
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I think the penny may have finally dropped at this end.
If we draw a timing diagram for the Amanero/S03/9018 in full sync mode we tend to assume that the output I2S outputs from the Amanero are time aligned with MCK. Quote:
Running the 9018 fully sync removes its ability to deal with these timing differences and so we drop data ? I don't have the equipment to prove this but ... Quote:
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#1002 |
diyAudio Member
Join Date: May 2002
Location: Madison, WI
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Dean -
I recall seeing your post, but only came away with the notion that you had gotten it working. Realize now that you had suggested the longer path and had speculated that your solution was totally serendipitous, based on the random choice of length of ufl MCK wiring. Is the little board pictured from Ian? Would hate to think that sync mode using the SO3 is not going to work unless we can test and then fab appropriate custom-length wiring. Come to think of it, however, I don't recall anyone other than you saying that full sync works with 90/98 clocks. :-( - Pat |
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#1003 | ||
diyAudio Member
Join Date: Jan 2008
Location: Sydney, Australia
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Quote:
I thought we already analysed this issue by taking it further with timing diagrams as show here: Quote:
@Pat, Can you try disconnecting Amanero from S03 board and see if the MCK of the Amanero is not active when connected to USB. This will indicate it is in Slave mode and ready to accept external MCK Simply measure the dc out on the MCK pin and this should be zero. If you see ~1.6 volts then MCK is active switching between 0 and 3.3V - This means the unit is not configured correctly
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AckoDAC Project Last edited by acko; 12th May 2014 at 09:29 PM. |
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#1004 |
diyAudio Member
Join Date: Jan 2008
Location: Sydney, Australia
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When all setup (before connecting to DAC) you can also use a scope to verify the outputs (Turbo MCK, BCK) and see if they match the timing diagram shown earlier
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AckoDAC Project |
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#1005 | |
diyAudio Member
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Quote:
I suppose the new firmware - "CPLD_1080_XC12, lrclk-sclk-data reduced delay." May make a difference when NOT reclocking. I will now sit in the corner of the room for a while ![]() |
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#1006 |
diyAudio Member
Join Date: May 2003
Location: Nis
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I will check what happens with clock signals when CPLD_1080_XC12 is flashed, because it doesn't work in slave mode.
Slave_for_1080 CPLD works, btclk_test and slave2224 works also and I'm only testing CPLDs for slave mode. Unfortunately I only have 200MHz,2Gs Rigol so my findings may not be complete (with relation to data signals as I can't see them all in the same time). |
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#1007 |
diyAudio Member
Join Date: Apr 2012
Location: Gamehendge
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I have an extra S01/S02 board from the original group buy if anyone wants it. To create synchronous mode you're going to need separate clocking unless you do P-Sync mode -- the Curryman 9023 board allows for this. Otherwise these boards are good for Async mode or just isolation. PM me if you're interested.
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#1008 |
diyAudio Member
Join Date: May 2006
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Can you clarify how the reclocking can work for 44.1 fs signal with a 100MHZ clock. Is it just that it will be close enough? If all you have is 44.1 is there another speed that is better for the reclocker using potato chips?
Thanks, Chris |
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#1009 |
Banned
Join Date: Sep 2012
Location: France
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OT, but is it possible to fight against a jittered input sended by a non clock slaved source ?
is it possible to reclock a multiplexed input with errors and abstract clean I2S from it ? i just can't understand the difference between both sota ACKO & IAN 's work ? Sorry for the lack of technical background, also interested by an input for the futur multiple construct threads which will born around TDA1541 soon. The cheaper the better... |
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#1010 | |
diyAudio Member
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Hi Acko,
I quote the post of palmito because I want use this configuration with my Doede's dac but I can't make it play music. Today I complete the board with the following setup: J1 - dedicate +5V J2 - not used J3 - dedicate +5V J4 - +3.3V from the dac J6 - not used R3 - 0R R4 - not used I check all the voltage as per schematic and are all there. You have any particular advice fot help me with the troubleshooting? I attach few pictures of the board and a small adapter for the dac input. I tested the adapter with the ohmmeter and look fine. In one picture I highlight a small bridge behind the board. I don't think this should shorted ? Thanks and Regards, Enrico PS: I reconnect the i2s directly from the rpi the DAC is working fine. Quote:
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