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Old 12th May 2014, 04:42 PM   #1001
deanoUK is offline deanoUK  United Kingdom
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Default Timing problems ?

I think the penny may have finally dropped at this end.

If we draw a timing diagram for the Amanero/S03/9018 in full sync mode
we tend to assume that the output I2S outputs from the Amanero are time aligned with MCK.

Quote:
Originally Posted by miksi View Post
For me Dsd files sounds weird and noisy with 1093 firmware. Will flash back 1080.
...
Something new came up, now we have CPLD_1080_XC12, lrclk-sclk-data reduced delay.
And I didn't tried 1082a yet.
When you think about it, they can not be as the I2S signals generated by the CPLD go through a number of gates in the CPLD and so will always be lagging wrt MCK (by how much I don't know).

Running the 9018 fully sync removes its ability to deal with these timing differences and so we drop data ?

I don't have the equipment to prove this but ...

Quote:
Originally Posted by deanoUK View Post
Got it working @ 90/98.
Attachment 365484 This is what makes it work, or at least a longer cable from the Si570 to the BuffaloIIIse.

The route for Si570 MCK through the acko AKL-AMN-S03 is longer than the route for Si570 MCK->BuffaloIIIse.

So a longer cable Si570->BuffaloIIIse compensates for the delay.
Worked.
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Old 12th May 2014, 05:10 PM   #1002
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Dean -

I recall seeing your post, but only came away with the notion that you had gotten it working. Realize now that you had suggested the longer path and had speculated that your solution was totally serendipitous, based on the random choice of length of ufl MCK wiring.

Is the little board pictured from Ian?

Would hate to think that sync mode using the SO3 is not going to work unless we can test and then fab appropriate custom-length wiring. Come to think of it, however, I don't recall anyone other than you saying that full sync works with 90/98 clocks. :-( - Pat
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Old 12th May 2014, 10:19 PM   #1003
acko is offline acko  Australia
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Quote:
Originally Posted by deanoUK View Post

When you think about it, they can not be as the I2S signals generated by the CPLD go through a number of gates in the CPLD and so will always be lagging wrt MCK (by how much I don't know).

Running the 9018 fully sync removes its ability to deal with these timing differences and so we drop data ?

I don't have the equipment to prove this but ...
Deano,

I thought we already analysed this issue by taking it further with timing diagrams as show here:
Quote:
Originally Posted by acko View Post
A quick analysis of the SO3 board timing with delays d1, d2 and a massively delayed d3 revels no issues with the data integrity. MCLK locks onto signal quickly and from there on everything is in step and aligned!
Also, your experiments with external Si570 and all the cable connections were done while waiting for the on-board XOs. I am not sure of the effect of cable lengths but if the delays are varying then the sync will be affected.

@Pat,
Can you try disconnecting Amanero from S03 board and see if the MCK of the Amanero is not active when connected to USB. This will indicate it is in Slave mode and ready to accept external MCK
Simply measure the dc out on the MCK pin and this should be zero. If you see ~1.6 volts then MCK is active switching between 0 and 3.3V - This means the unit is not configured correctly
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Last edited by acko; 12th May 2014 at 10:29 PM.
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Old 12th May 2014, 11:58 PM   #1004
acko is offline acko  Australia
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When all setup (before connecting to DAC) you can also use a scope to verify the outputs (Turbo MCK, BCK) and see if they match the timing diagram shown earlier
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Old 15th May 2014, 05:17 PM   #1005
deanoUK is offline deanoUK  United Kingdom
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Quote:
Originally Posted by acko View Post
Deano,
I thought we already analysed this issue by taking it further with timing diagrams as show here:
Sorry, jumped the gun there. Posted without engaging brain.
I suppose the new firmware -
"CPLD_1080_XC12, lrclk-sclk-data reduced delay."
May make a difference when NOT reclocking.

I will now sit in the corner of the room for a while
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Old 15th May 2014, 07:04 PM   #1006
miksi is offline miksi  Serbia
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I will check what happens with clock signals when CPLD_1080_XC12 is flashed, because it doesn't work in slave mode.
Slave_for_1080 CPLD works, btclk_test and slave2224 works also and I'm only testing CPLDs for slave mode. Unfortunately I only have 200MHz,2Gs Rigol so my findings may not be complete (with relation to data signals as I can't see them all in the same time).
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Old 16th May 2014, 07:04 AM   #1007
Mull3t is offline Mull3t  United States
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I have an extra S01/S02 board from the original group buy if anyone wants it. To create synchronous mode you're going to need separate clocking unless you do P-Sync mode -- the Curryman 9023 board allows for this. Otherwise these boards are good for Async mode or just isolation. PM me if you're interested.
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Old 16th May 2014, 04:02 PM   #1008
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Quote:
Originally Posted by acko View Post
Yes, this should work fine for tda1541a or other DACs
Can you clarify how the reclocking can work for 44.1 fs signal with a 100MHZ clock. Is it just that it will be close enough? If all you have is 44.1 is there another speed that is better for the reclocker using potato chips?

Thanks,
Chris
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Old 16th May 2014, 04:17 PM   #1009
Eldam is offline Eldam  France
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Location: At home, sweet sound home...
OT, but is it possible to fight against a jittered input sended by a non clock slaved source ?

is it possible to reclock a multiplexed input with errors and abstract clean I2S from it ?

i just can't understand the difference between both sota ACKO & IAN 's work ?

Sorry for the lack of technical background, also interested by an input for the futur multiple construct threads which will born around TDA1541 soon.

The cheaper the better...
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Old 17th May 2014, 10:13 AM   #1010
emyeuoi is offline emyeuoi  Italy
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Default I need some help with the reclocker board

Hi Acko,

I quote the post of palmito because I want use this configuration with my Doede's dac but I can't make it play music.

Today I complete the board with the following setup:
J1 - dedicate +5V
J2 - not used
J3 - dedicate +5V
J4 - +3.3V from the dac
J6 - not used

R3 - 0R
R4 - not used

I check all the voltage as per schematic and are all there.

You have any particular advice fot help me with the troubleshooting?

I attach few pictures of the board and a small adapter for the dac input. I tested the adapter with the ohmmeter and look fine.

In one picture I highlight a small bridge behind the board. I don't think this should shorted ?

Thanks and Regards,
Enrico

PS: I reconnect the i2s directly from the rpi the DAC is working fine.



Quote:
Originally Posted by palmito View Post
I had a few emails with Akco on configuring the S03 for Doede's dac and thought anyone attempting this would benefit from a quick write up. I've also included a diagram of my setup. The questions in italics are mine, the boldfaced answers are Acko's.

1) The PCM1794 generates its own clock from BCK? So the MCK line from the S03 is ignored?

Yes, no external MCK is required for PCM1794

Now for the fine tuning, if you look at the "App Notes", your setup falls into the "Aysnc Mode with isolated connection and re-clocking" (Page 4).-The Pi replaces "Amanero" in this case. Pi and DAC are running on their own clocks and SO3 board has its own ref clock. With Async mode it would be preferable increase the frequency of the SO3 clock to 100MHz to reduce pulse modulation errors and you just need one XO for this case. There is also no need to use synchronous types like 98.304MHz since the operation is Async. Try mounting a CCHD575 100MHz and see how it sounds.

Later on he added this:
I indicated to you before the with your SO3-PCM DAC, the mode is Asynchronous based on your last setup. Actually, it is Synchronous drive as the PCM1794 uses the Bit Clock as it's Master Clock reference. So all good here for the best performance

2) You suggested the 100mhz CCHD575. In the FIFO thread Ian suggested the CCHD-950 (Mouser). Could you compare the two and recommend one?
CCHD575 has the lowest phase noise but if you have CHD950 100MHz, this is fine, it is not too far behind.

3) On going with a higher than 100mhz clock rate xo, since Doede's dac doesn't use MCK so you are shooting for the lower jitter and pulse modulation error which would have an effect on BCK, which is used by the dac chip to generate MCK Acko commented:

There is of course nothing stopping you from going higher ( up to 600MHz for the Potsemi chips) to see if there are further benefits so long as low jitter XOs are chosen.

4) Does it matter what position on the S03 board the single 100mhz clock goes, X1 or X2?
For single fixed XO operation, you will need to mount it on X1 position. Also make sure that R18 (near 'SEL') is mounted to act as a pull down. This will enable X1 (and disable X2).

5) About trying batteries instead of the three regulator choices Acko gives you:
Yes, you can try with batteries and see if it improves over the LTC6655 reg on-board. Also try a 6V LiFePO4 powering the reg circuit

6) I asked the following question after putting R18 in and the 100mhz clock because if I decide to try to power the clock with a LiFePO4 battery I don't want to be powering the X2 clock if I'm not using it (needless drain of the battery):
R18 takes X2 out of the circuit, so it's not powered?
Will still be powered but output disabled and in highZ.

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