Greetings Ian
I'm getting ready to start testing the gear.
I think I've got this straightened out for going dual mono with my build
The 12s output and clock need to be spliced out to go to the 2 dac inputs. The wires are strongly recommended to be of the same length. Your buf3 adapter kits should be a good fit for this configuration. So one kit would be used to split the sgnal from the fifo/clock gear while 2 kits would be used to connect the 12s signal to the 2 dacs.An extra kits would be required if using sidecar. Does this make sense?
If this is the case, I will have to order extra buf3 adapters and uf.l connectors. Can you supply these items?
other question, does the i2s backdoor support 32bit 384khz signal?
This is the build process I will be using:
1a) build dac with vanilla single dac and ttl input direct to dac
1b) implement spdf fifo kit
2) implement hifiduino controller
3) implement sync/async clock tweak on buf3 dacs
4) implement dual mono configuration
regards.
I'm getting ready to start testing the gear.
I think I've got this straightened out for going dual mono with my build
The 12s output and clock need to be spliced out to go to the 2 dac inputs. The wires are strongly recommended to be of the same length. Your buf3 adapter kits should be a good fit for this configuration. So one kit would be used to split the sgnal from the fifo/clock gear while 2 kits would be used to connect the 12s signal to the 2 dacs.An extra kits would be required if using sidecar. Does this make sense?
If this is the case, I will have to order extra buf3 adapters and uf.l connectors. Can you supply these items?
other question, does the i2s backdoor support 32bit 384khz signal?
This is the build process I will be using:
1a) build dac with vanilla single dac and ttl input direct to dac
1b) implement spdf fifo kit
2) implement hifiduino controller
3) implement sync/async clock tweak on buf3 dacs
4) implement dual mono configuration
regards.
Last edited:
Hi necplusultra,
Using a BIII adapter to branch the I2S signals into the two ESS DACs is a very smart idea. I didn't think of it. And there are already two U.FL MCLK output sockets on the dual clock board for the dual mono sync mode.
Yes,you can order the additional BIII adapter PCB and the cables now. Since you are in Canada, the shipping would be only $1- if I mail them as a letter. Please just send the order form to me if you want.
I2S back door support 384KHz, but with the 49.xxxMHz XO, you could get only 128*Fs MCLK, that's no problem for async mode, but might be problem for sync mode with ESS DAC( need 256*fs or more).
Please let me know your progress.
Ian
Thank you veeery much , Ian !
just finished my FIFO . it`s integrated with dual-mono Opus Dac .... and with these generic XO`s (i`m waiting for 1ppm , -135dB phase noise TCXO`s from ebay...) it sounds unbelievably good (my setup is : PC based linear powered CMP player , BAT VK30 +VK200 and Audio Physic New Tempo) and i must say again : THANK YOU VERY MUCH ,IAN !!!! BTW : where are my rubber rings ?!
)))
just finished my FIFO . it`s integrated with dual-mono Opus Dac .... and with these generic XO`s (i`m waiting for 1ppm , -135dB phase noise TCXO`s from ebay...) it sounds unbelievably good (my setup is : PC based linear powered CMP player , BAT VK30 +VK200 and Audio Physic New Tempo) and i must say again : THANK YOU VERY MUCH ,IAN !!!! BTW : where are my rubber rings ?!
)))
just finished my FIFO . it`s integrated with dual-mono Opus Dac .... and with these generic XO`s (i`m waiting for 1ppm , -135dB phase noise TCXO`s from ebay...) it sounds unbelievably good (my setup is : PC based linear powered CMP player , BAT VK30 +VK200 and Audio Physic New Tempo) and i must say again : THANK YOU VERY MUCH ,IAN !!!! BTW : where are my rubber rings ?!
Congratulations Sernikus! You will get more surprise if you run the FIFO with really nice low jitter clocks.
I didn't supply rubber rings this time. Beacuse the ones I sourced were not good enough, very easy to be broken. Here are some possible solutions, just for reference:
http://www.diyaudio.com/forums/grou...s-pdif-fifo-kit-group-buy-21.html#post3002222
Good luck to your projcet.
Ian
Hi Ian
After spending some time on Spidf board and finally opening The I2S Backdoor, well that was really pretty small bit of soldering...
Have some questions regarding SPIDF board, hope that OK for GB thread.
Would You advice way of "moding" SPIDF board TTL input to adapt Coax Level Spidf , preferably with PE Trafos ...
Specially that at the moment I do not have any need for Spidf Ouptut, so can use PE separation trafos from output part.
Hope than not only for me having second Coax In is more interesting than TTL IN.
Regards
Rosendorfer
After spending some time on Spidf board and finally opening The I2S Backdoor, well that was really pretty small bit of soldering...
Have some questions regarding SPIDF board, hope that OK for GB thread.
Would You advice way of "moding" SPIDF board TTL input to adapt Coax Level Spidf , preferably with PE Trafos ...
Specially that at the moment I do not have any need for Spidf Ouptut, so can use PE separation trafos from output part.
Hope than not only for me having second Coax In is more interesting than TTL IN.
Regards
Rosendorfer
Hi Ian
Do You have free just Duall Clock board, I'm thinking about buying second one.
It is that good that having just one is not enough.
Regards
Rosendorfer
yes, I still have some dual xo clock boards available. I can ship it in a envelope, the shipping would be much less. Just send me the order form if you want.
Regards,
Ian
Good to know you made it. Actually it's not that difficult, if you do a second one
.TTL input and coaxial input are different. Coaxial comes with a AC coupled RF amp, while TTL is just a LVTTL input with schmitt trigger. TTL S/PDIF input is usefull to interface with device such as a CD/DVD ROM. I remember TP has a hi-speed comparator solution which could converte coaxial S/PDIF into TTL signal, if I'm not wrong. It might be a good reference.
Regards,
Ian
Hi Ian,
While I'm waiting to receive FIFO buffer, just a clarification using it with I2S input from CD-PRO2 and feeding SM5842/PCM63:
- jumper TP48 open, so MCLK is 256*fs, 11.2896 MHz
- jumper TP43 short to ground, left justified to feed SM5842
- jumpers TP41 and TP42 open, I2S 16/32 bit feeding from Philips CD-PRO2
Is that right?
A few questions:
- I'm building a low phase noise oscillator to use as external clock for FIFO buffer. Is 11.2896 the right frequency to synchronize I2S from CD-PRO2 with FIFO buffer and then SM5842?
- SM5842 system clock (XTI pin): it accept 256fs or 348fs, so I have to use 256fs directly external clock, right?
- SM5842 input bitclock (BCKI pin): need 64fs (2.8224) as the I2S signal clock, so I have to connect SCK of the I2S output cable from the FIFO buffer, right?
- SM5842 data input (IW1L/DIL and IW2N/DIR pin): I think I have to configure input data as "LR alternating, leading data" with INF1N pin high and DI/INF2N pin low, so I can connect SD of the I2S output cable from the FIFO buffer to both L/R data input, right?
- SM5842 sample rate clock (LRCI pin): need fs clock, so I can connect WS of the I2S output cable from the FIFO buffer, right?
- no other connections from FIFO buffer to SM5842, right?
Thanks for the great job.
Andrea
While I'm waiting to receive FIFO buffer, just a clarification using it with I2S input from CD-PRO2 and feeding SM5842/PCM63:
- jumper TP48 open, so MCLK is 256*fs, 11.2896 MHz
- jumper TP43 short to ground, left justified to feed SM5842
- jumpers TP41 and TP42 open, I2S 16/32 bit feeding from Philips CD-PRO2
Is that right?
A few questions:
- I'm building a low phase noise oscillator to use as external clock for FIFO buffer. Is 11.2896 the right frequency to synchronize I2S from CD-PRO2 with FIFO buffer and then SM5842?
- SM5842 system clock (XTI pin): it accept 256fs or 348fs, so I have to use 256fs directly external clock, right?
- SM5842 input bitclock (BCKI pin): need 64fs (2.8224) as the I2S signal clock, so I have to connect SCK of the I2S output cable from the FIFO buffer, right?
- SM5842 data input (IW1L/DIL and IW2N/DIR pin): I think I have to configure input data as "LR alternating, leading data" with INF1N pin high and DI/INF2N pin low, so I can connect SD of the I2S output cable from the FIFO buffer to both L/R data input, right?
- SM5842 sample rate clock (LRCI pin): need fs clock, so I can connect WS of the I2S output cable from the FIFO buffer, right?
- no other connections from FIFO buffer to SM5842, right?
Thanks for the great job.
Andrea
Hi Ian,
I was in the GBII list but did not make the payment yet (I have been just outside of the country for business).
Do please let me know if I still can fulfill my payment and have everything sent. (my order contains only BuffIII adapters and some other connectors).
Best regards
Pepe
I was in the GBII list but did not make the payment yet (I have been just outside of the country for business).
Do please let me know if I still can fulfill my payment and have everything sent. (my order contains only BuffIII adapters and some other connectors).
Best regards
Pepe
Last edited: