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Old 16th October 2012, 12:42 AM   #641
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Quote:
Originally Posted by iancanada View Post
Hopefully I could list the isolator board PCB and the battery management PCB in GB III.

Ian
What are the criteria for reaching critical mass for a GB run of the Si570 clock board Ian?
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Old 16th October 2012, 03:30 AM   #642
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N02. spm I2S FIFO,Dual XO Clock board,S/PDIF Interface Board,2x SMT U.FL,8x 6",4x 12”,I2S backdoor KIT, 2xXO Adapters lot of 5,2xBIII adapters,2x SMT connector package
N08. mfrimu 1*I2S FIFO KIT 1*Dual XO Clock board 1*S/PDIF Interface
N09. makumba1966 1*I2S FIFO KIT, 1*Dual XO Clock board , 1*S/PDIF Interface, 4 x BIII adapter, 1x I2S backdoor KIT for S/PDIF board, 2x Package of Universal SMT XO Adapters KIT lot of 5, 4x Additional BIII adapters PCB, 4x SMT connector package for BIII adapters Board
N10. LuisMCP - 1 x I2S Kit + 1 x Dual XO
N11. number9 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x S/PDIF Interface
N12. Fridrik 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x S/PDIF Interface 2x Universal SMT XO Adapters KIT, 1x I2S backdoor KIT
N13. jwkim 1 * I2S FIFO KIT 1 * Dual XO Clock board 1 * S/PDIF Interface Board 1 * I2S backdoor KIT for S/PDIF
N14. dsdjoy, 3 x BIII Adapters PCB, 3 x SMT Connector for BIII adapters, 12 x SMT U.FL Socket, 4 x 4" coaxial cable 50ohm, 4 x 6" coaxial cable 50ohm
N15. hangguy 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x S/PDIF Interface, 5x SMT U.FL socket, 3x 6" coxial cable, 1x Universal XO adapters, 1x SMT connector package for BIII adapters
N16. Sachi 1 * I2S FIFO KIT 1 * Dual XO Clock board 2*BIII adapter and connectors
N17. Finaxe 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x S/PDIF Interface 2x Universal SMT XO Adapters KIT, 1x I2S backdoor KIT
N18 Tagheuer 1x I2S FIFO Kit, 1x Dual XO Clock Board, 2 x BIII Adapters PCB, 3 x SMT Connector for BIII adapters, 1x Universal XO adapters, 12 x 4"double-ended U.FL coaxial cable
N19. palmito 1 x I2S FIFO KIT, 1 x Dual XO Clock board, 1 x S/PDIF Interface Board, 1 x I2S backdoor KIT for S/PDIF board, 4 x 4" coaxial cable 50ohm
N20. Keith Taylor 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x SPDIF Interface Board
N21. marcus1 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x S/PDIF Interface, 2x Universal SMT XO Adapters KIT, 1x I2S backdoor KIT
N22 Joonas 1 x I2S FIFO kit and 1 x S/PDIF interface board
N23 Stasiope 1 x I2S FIFO KIT, 1 x Dual XO Clock board, 1 x Package of Universal SMT XO Adapters, 1 x Additional BIII adapters PCB, 1 x SMT connector package for BIII adapters, 3x 4” double-ended 50 ohm coaxial cable
N24 chi0001 1 x I2S FIFO KIT 6 x 4" Cables 1 x Dual clock board
N25 rsotirov 1x I2S FIFO Kit, 1x Dual XO Clock Board, 1x S/PDIF Interface, 2x
Universal SMT XO Adapters KIT, 1x I2S backdoor KIT
N26. miksi, 2 x BIII Adapters PCB, 2 x SMT Connector for BIII adapters, 20 x SMT U.FL Socket, 4 x 4" coaxial cable 50ohm, 4 x 6" coaxial cable 50ohm, 4 x 12" coaxial cable 50ohm
N27 hirez69, 1 x I2S FIFO KIT, 1 x Dual XO Clock Board, 1 x Universal SMT XO Adapters KIT, 4 x BIII Adapters PCB, 1x S/PDIF Interface, 1x I2S backdoor KIT
N28 hochopeper, 1 x I2S FIFO KIT, 1 x Dual XO clock board, 1 x universal SMT XO ADAPTERS KIT, 8 x 4" coax cables
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Old 16th October 2012, 10:30 AM   #643
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Quote:
Originally Posted by hochopeper View Post
What are the criteria for reaching critical mass for a GB run of the Si570 clock board Ian?
Why SI570? It seems not very suitable for audio application.
It's a VCXO using a PLL, usually not the best way for audio clock.
But PLL aside, they declare in the datasheet a phase noise of -112dBc@100Hz for 120 MHz frequency. Considering -6dBc/octave of phase noise reduction (that's optimistic, not always true) you can get (optimistically) -130dBc@100Hz for 15MHz frequency. A very good oscillator shows a phase noise of -130/-135dBc at 10 Hz, and about -150dBc at 100Hz, and for audio application it's more important the phase noise at 1 and 10Hz rather than 100Hz or more.
See the specification of the OCXO I have ordered as a sample from HCD.

So, I think the best way could be using an expensive OCXO, or better building a discrete good XO starting from a very good AT-cut crystal.
I also believe we can get better phase noise performance than SI570 using a simple oscillator with an unbuffered logic inverter such as 74HC04 and a 0.4 USD crystal from Citizen.

Andrea
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File Type: pdf hcd661.pdf (41.2 KB, 38 views)
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Old 16th October 2012, 11:30 AM   #644
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andrea, I have to disagree that it is not suitable, if you follow the FIFO r&d thread you'll notice Ian has been testing the Si570, with positive initial results. I am interested to try it because I like the flexibility in selecting frequencies and experimenting. Why does everyone seem so up in arms about trying something like the Si570, it's been used successfully a few times in other projects already and Ian's implementation of it looks very neat. I think it would be best to continue this conversation out of the GB thread, if necessary.

My question is still simply, for the board which Ian is now onto his 2nd revision design (I think it's second of his revisions plus his testing with the Si570 dev kit), what qty of interest is necessary to make it viable for a group buy after he is happy with the device's implementation.
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Old 16th October 2012, 11:58 AM   #645
qusp is offline qusp  Australia
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Andrea: I think you are both overly critical and overly optimistic. You are not the first to briefly gaze 'knowingly' at the datasheet and declare it unsuitable, perhaps you should look back over those conversations to find the outcome, or perhaps look at why its desirable… which seems to have escaped you given your recommendations. Better yet, question why it matters to you at all? dont think its suitable, dont buy it …

Last edited by qusp; 16th October 2012 at 12:01 PM.
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Old 16th October 2012, 01:08 PM   #646
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Hochopeper, Qusp,

A low phase noise (noise in frequency domain) does not guarantee low jitter (noise in time domain), but high phase noise surely guarantees high jitter, since phase noise influences jitter performance, or noise in time domain is strongly affected by noise in frequency domain (mathematically demonstrated).

I simply said that SI570 don't show good performance in phase noise, so we can reach the same or better performance with a simple and inexpensive oscillator like in the attacched document (a little more than 1 USD to get a SN74LVC1404, a crystal from the bookshelf, 2 NP0 capacitor and 2 resistors).
With about 3 USD you can build 2 oscillator with at least the same performance of the SI570 (designed for other application) that costs 65 USD. Also if you make a selection from a bag of low cost crystal like Citizen by listening you can get better performance.
Replacing the crystal from the bookshelf with a cold welded HC-49 custom AT-cut crystal with a very high Q (>100k or better), you can easily reach -125dBc@10Hz phase noise or better.

I think Ian's FIFO project is an excellent project, so it need an excellent clock.

Andrea
Attached Files
File Type: pdf IC CRYSTAL OSCILLATOR CIRCUITS.pdf (443.8 KB, 48 views)
File Type: pdf sn74lvc1404.pdf (662.5 KB, 27 views)
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Old 16th October 2012, 01:31 PM   #647
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Quote:
Originally Posted by andrea_mori View Post
Hochopeper, Qusp,

A low phase noise (noise in frequency domain) does not guarantee low jitter (noise in time domain), but high phase noise surely guarantees high jitter, since phase noise influences jitter performance, or noise in time domain is strongly affected by noise in frequency domain (mathematically demonstrated).

I simply said that SI570 don't show good performance in phase noise, so we can reach the same or better performance with a simple and inexpensive oscillator like in the attacched document (a little more than 1 USD to get a SN74LVC1404, a crystal from the bookshelf, 2 NP0 capacitor and 2 resistors).
With about 3 USD you can build 2 oscillator with at least the same performance of the SI570 (designed for other application) that costs 65 USD. Also if you make a selection from a bag of low cost crystal like Citizen by listening you can get better performance.
Replacing the crystal from the bookshelf with a cold welded HC-49 custom AT-cut crystal with a very high Q (>100k or better), you can easily reach -125dBc@10Hz phase noise or better.

I think Ian's FIFO project is an excellent project, so it need an excellent clock.

Andrea
I agree! Ian's FIFO project deserve a much better clock than Si570.
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Old 16th October 2012, 02:45 PM   #648
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Lets not forget the design goal of the Si570 board: multiple frequencies. For those wanting the ultimate in phase noise, you can still use the dual-clock board.
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Old 17th October 2012, 12:13 AM   #649
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Lets not forget the design goal of the Si570 board: multiple frequencies. For those wanting the ultimate in phase noise, you can still use the dual-clock board.
indeed it seems some are a bit slow on the uptake around here.... numbers are in fact better than cchd950, still not quite as good as cchd957, but able to do speeds not available for this clock. MUCH better when talking of less than 1ps on all 3 is the sort of language that gets audiophiles laughed at


as for dual clock board, yes, they can and I can.... along with the cchd957 clocks I already have for it. I have no desire to buy the NDK just to get the higher speeds I need, when frankly in the greater scheme of things the difference is...... I would also like to experiment with even faster speeds running NOS mode on ESS, perhaps using some sort of external hardware digital filter, the ability to change speeds at will to try all of these and attain speeds not available any other way other than building a multiplier of your own each time is pretty sweet in my world.

do you guys work for NDK or something? pretty much the only real competition before mortgaging the house and still not adjustable. come on, show us your adjustable DIY xxxfS clock designs?

Last edited by qusp; 17th October 2012 at 12:24 AM.
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Old 17th October 2012, 12:32 AM   #650
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Originally Posted by qusp View Post
indeed it seems some are a bit slow on the uptake around here.... numbers are in fact better than cchd950, still not quite as good as cchd957, but able to do speeds not available for this clock. MUCH better when talking of less than 1ps on all 3 is the sort of language that gets audiophiles laughed at
You know I agree with you here.

I think it would be nice if people who have a totally different world view and are not in the market for ESS DACs with high freq mclk would show some respect, in much the same way as I don't fully comprehend the nuances in the motivation for persisting with PCM & NOS DACs and their application ... though I don't go commenting on those subjects.

Regardless, Ian has addressed my original question in the R&D thread regarding numbers required for a GB run of his design for those that are interested. Thank you Ian!

Last edited by hochopeper; 17th October 2012 at 12:40 AM.
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