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Old 20th September 2011, 11:31 AM   #761
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Originally Posted by Marek View Post
You still forget that AD1865 is 18-bit DAC and what you need to delay is not LRCLK but DATA line by 32-1-18 cycles...
No, I'm just ignoring it

My next dac project will take this problem into account though. As for now I'll just live with a non bit perfect dac.
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Old 20th September 2011, 11:43 AM   #762
Marek is offline Marek  Poland
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non bit-perfect?? Its not my point!
When you delay LRCK by 1 clock you will cut a few MSBs! thats why you get clipping! currently you squash your audio into few LSBs so you get less than 10bit audio!
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Old 20th September 2011, 12:02 PM   #763
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non bit-perfect?? Its not my point!
When you delay LRCK by 1 clock you will cut a few MSBs! thats why you get clipping! currently you squash your audio into few LSBs so you get less than 10bit audio!
So what you're saying is that if the timing requirements for LE and BCK is correct, you still couldn't feed the dac with a 16-bit signal in a 32-bit data stream? I had the impression that the dac only latched in the last 18-bits of the data stream after LE goes low.

Problem here is that LE goes low one cycle too early.
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Old 20th September 2011, 12:08 PM   #764
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You have to latch *FIRST* 18bit DATA (18 most significant bits of 32bit word) so when you delay *DATA* by 32-1-18 cycles the *falling* edge of LRCLK will latch theme.
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Old 20th September 2011, 05:14 PM   #765
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You have to latch *FIRST* 18bit DATA (18 most significant bits of 32bit word) so when you delay *DATA* by 32-1-18 cycles the *falling* edge of LRCLK will latch theme.
Ok, I get it now. The audio bits lie in the beginning of the I2S data stream, and the AD1865 only latches the last 18 bits. So with a 16 bit audio signal, only the two least significant bits would be latched.

What I find really interesting is that when I attenuate the signal digitally by 78 dB in the software I get a normal output signal. Definitely more than ten bits. 78 dB attenuation equals dividing the signal by ~2^13, or the same as shifting the data 13 bits to the right.

It's a surprising result to me. But it works!
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Old 21st September 2011, 01:31 AM   #766
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Originally Posted by Painkiller View Post
What I find really interesting is that when I attenuate the signal digitally by 78 dB in the software I get a normal output signal. Definitely more than ten bits. 78 dB attenuation equals dividing the signal by ~2^13, or the same as shifting the data 13 bits to the right.
So long as the software is working with the full 24bits and the exa handles the full 24bits then this is correct. Why not use digital attenuation to set the correct bit position for your DAC? As you say, it works! But with a 13 bit shift of a 24 bit signal your DAC must be only receiving 11 bits. Or is the software actually working at 32bits? In which case there's no problem at all, your DAC will be getting sent 19 bits (but natually ignoring one of them).
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Old 21st September 2011, 06:23 AM   #767
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So long as the software is working with the full 24bits and the exa handles the full 24bits then this is correct. Why not use digital attenuation to set the correct bit position for your DAC? As you say, it works! But with a 13 bit shift of a 24 bit signal your DAC must be only receiving 11 bits. Or is the software actually working at 32bits? In which case there's no problem at all, your DAC will be getting sent 19 bits (but natually ignoring one of them).
The software actually works at 64 bits, but the datastream sent to the exa is 32 bits. The correct amount of shifting would be 14 bits minus 1 bit, since the LRCK in the I2s stream goes low one cycle too early for the dac. So 13 bits should be just about right. That equals 78.26779887... dB
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Old 21st September 2011, 07:28 AM   #768
Marek is offline Marek  Poland
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Painkiller,

Now you are absolutely right.
You can use 2pcs of 8bit flip flop with pararell output - so you can easy set right delay by choosing coresponding output pin Qx. This solution works very good.
And ofcourse additionally you have to negate LRCLK to provide latch signal to second channel.
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Old 23rd September 2011, 10:42 AM   #769
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Got my name on the waiting list.

Anybody know what the timeframe is?

thanks
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Old 23rd September 2011, 11:43 AM   #770
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Painkiller,

Now you are absolutely right.
You can use 2pcs of 8bit flip flop with pararell output - so you can easy set right delay by choosing coresponding output pin Qx. This solution works very good.
And ofcourse additionally you have to negate LRCLK to provide latch signal to second channel.
I'm still worried about the propagation delay of these IC's, when running 192 kHz. With only two of these shift registers, you're around 24 ns delay, and close to getting timing errors. That means you should consider delaying all the other digital lines with nand gates also. Or else you need additional reclocking. It's not supposed to be easy. Bit shifting by accurate volume leveling in the software is the easiest solution yet.
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