This was not completely accurate...
60dB is a calculated maximum possible improvement on the bit clock as a theoretical worst case scenario.
A 1ps jitter clock vs a 2ns variation of the GMR´s,
but as an example with a ES9018 chip this would have little or barely no effect at all as only the jitter on the word clock would matter as long as the correct "0" and "1" data bits are clocked in..
What matters on a ES9018 are the word clock.
Jitter on the word clock will be mostly removed by the ES9018 jitter removal circuit.
Also on a PCM1704 the bit clock are only used to shift the data into a serial buffer and it is the word clock that would be sensitive for jitter.
The word clock latches the data from the serial buffer into a parallel buffer for further processing.
The word clock will only be affected of 1/64 times of the jitter a GMR isolator might introduce compared to the bit clock.
With a PCM1704 without any jitter removal circuit this may make a difference compared to a ES9018 where any jitter will be greatly reduced.
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Do you have empirical evidence of this or are you just believing the ESS marketing department? Have you heard any difference between GMR isolator in circuit & out of circuit?
Hello Kazap,
I will speculate that it will sound better without the DSP-1. You will know for sure after you try it both ways and ask your wife for a blind test
. It is easy to assign 4 left and 4 right channels with the exaU2I ASIO driver. Later today I will read about PCM1704 to see if a little firmware modification is required to have a clean solution and to make your life simpler.
Cheers,
eha065
I was trusting in your statement in the first "quote" was empirical evidence
Maybe the "negative sonic impact" you states are caused by something else than "jitter" when YOU experience the phenomenon
Even if you states
I would recommend that you evaluates what USB galvanic isolation will do first....
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Here we go again
Sorry, yes I forgot I posted about this already - I'm outta here!
Maybe others will give their opinion based on bypassing the isolators?
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It appear a bit strange when you switches your arguments when you have forgotten what you argument was against / for the last time you posted ??
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Sorry EXA but RayCtech has to be answered!
What? I'm not switching arguments? Maybe you don't understand?
As I sated before - GMR isolators in the I2S lines degrade the sound, probably as a result of their added jitter & the jitter reduction of the Sabre DAC will not negate this (no matter what ESS marketing says). No different from what I said before except for the ESS bit added in.
What? I'm not switching arguments? Maybe you don't understand?
As I sated before - GMR isolators in the I2S lines degrade the sound, probably as a result of their added jitter & the jitter reduction of the Sabre DAC will not negate this (no matter what ESS marketing says). No different from what I said before except for the ESS bit added in.
Hi John,
I don't want you to abandon the thread. I just need to avoid opening again topics where we agreed to disagree. There are plenty of devices without GMRs. People can also remove the GMR's from the exaU2I and decide for themselves if there is more gain or more loss.
Regarding the ESS advertising, I am amazed how silly are the attacks against the capabilities of their jitter removal technology. I speak here as a DIY person. ES 9018 is one of the best things that happen to my personal system for the past 20 years. Perhaps people have disappointments with their product because they don't have the specifications and the knowledge to use it properly.
The real exaU2I jitter is less than the calculated about 100ps. And there is more to exaU2I than jitter. It is a fine package that delivers clean, dynamic and detailed sound. We haven't had a single user saying that the for the improvement it brings the board is too expensive. I fact all of our users are enthusiastic about exaU2I.
Regards,
exa065
Sure, & maybe some users of the EXA will try bypassing the GMR device & reporting their sonic findings?
Maybe you missed this post http://www.diyaudio.com/forums/digi...g-new-ess-vout-dac-es9022-13.html#post2550015
And the extract by some ex-design engineers of the ESS
Sure, Exa, I don't doubt about what you say.
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Kazap,
Unfortunately it is impossible to connect exaU2I directly to PCM1704. PCM1704 expects data in "Standard Format (Sony Format), right justified". The exaU2I output is I2S. You need to use DF1704 as in intermediate step. DF1704 accepts one stereo I2S feed and supplies two PCM1704 mono DACs.
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Yes, its true, but it is possible with some simple glue logic. Look here: Creating a DIY non oversampling DAC with PCM1704
All you have to do is to delay DATA line properely for each PCM1704 chip. Universal and the most elegant solution is use of variable delay flip flop chip (eg CD4557) for every DAC chip. This solution can be used with every ladder DAC - 16,18,20 and 24-bit - you only have to set right delay using dip-switches.
Another advantage of this solution is that the circuit works on DATA line only so its intristic jitter do not apply to clock lines - there is absolutely no performance degrade.
In case of PCM1704 it is not true.The clock which is sensitive for jitter is BCLK because analog value is updated on SECOND rising edge of BCLK after WCLK goes down.
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This is an interresting approach. I have two AD1862 20-bit dac chips which I intend to make into a DIY project. The AD1862 seems to clock in the last bit one bitclock cycle earlier than according to the I2S specification. So the data has to be delayed by (wordlength - 20 - 1) number of bitclock cycles.
Does the exaU2I wordclock run at 64xFs regardless of the chosen bit depth? In that case the data would have to be delayed 11 cycles for both channels and an additional 32 cycles for the right channel.
Yes you're right.
I'm using this circuit with NON-OS DAC based od AD1865 (18-bit) and I play high sampling freq. tracks in non-os mode. Sweet
Yes, exaU2I wordclock always runs at 64xFs. The bit depth is always 32bit.
Yes you're right.
I'm using this circuit with NON-OS DAC based od AD1865 (18-bit) and I play high sampling freq. tracks in non-os mode. Sweet
That sounds like a real treat.
But won't the chip be more susceptible to jitter when running a higher sampling frequency?How do you wire the CD4557 chip to achieve the right amount of delay? I have to admit I didn't understand much from the datasheet.
I was wondering, on your website you note "Resolution (bits) 16 to 32"
For my application i need word widths of 16, 18, 20 and 24 bits.
Is this not possible ?
I was wondering, on your website you note "Resolution (bits) 16 to 32"
For my application i need word widths of 16, 18, 20 and 24 bits.
Is this not possible ?
Word widths on the ASIO input can be anything from 8 to 32bits packaged in a standard ASIO 32bit envelope. The ASIO driver asks the player application for data packaged in 32bit envelope. The I2S output is always 32bit.