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Old 10th June 2016, 06:05 PM   #1371
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Join Date: Feb 2015
Anyone knows why the choice was made to add isolation after the buffering and reclocking, instead of isolating the I2S extracted from USB and then buffer in the FPGA and read out with high quality clock as it is done?

The isolation adds its own jitter if i understand
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Old 10th June 2016, 07:17 PM   #1372
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Join Date: Aug 2002
Location: Cascais
Originally Posted by jojip View Post
Anyone knows why the choice was made to add isolation after the buffering and reclocking

It's been ages since i had one of those, but is there any actual reclocking outside of the processor? I guess isolating and reclocking 8 channels would have added quite a bit of complexity to the board. And there was supposed to be a mk2...
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Old 11th June 2016, 07:40 PM   #1373
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There is no reclocking on this board. But USB data is decoupled into a large buffer inside the FPGA and read out using high quality clocks on the board. However the power domain isolation happens on the output I2S interface using GMRs which inject jitter of their own.

Wonder why the USB power isolation wasnt done at the input, leaving the I2S output to have the low jiiter clock
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Old 13th January 2017, 06:45 AM   #1374
aradan is offline aradan  Singapore
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Join Date: Apr 2015
Location: Born in Russia, living in Singapore
Originally Posted by reactivepower View Post
Does anyone know if drivers are still available for this BTW? Just upgraded to Win 10 in my second compost and wondering if there is a compatible driver for it. The old site appears to be down.
You should reach out to their email address on the web site. To get for access and drivers

Sent from my F8332 using Tapatalk
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