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Old 25th February 2011, 12:30 AM   #91
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The LR clock works at the sample frequency and basically says 'when this clock is on the data at the moment is for the left channel (or right channel I'm not sure which) and visa versa.

The Data stream carries a stream of 1's and 0's, this contains the information of the digital signal that is to be converted into analogue.

The Bit clock is the clock used to time and decode the data stream and usually operates at 64x fs. In other words the bit clock is high, check data stream for it's polarity, okay, it's a 0. Bit clock goes low, look again at the data stream, okay its another zero. Without the bit clock doing the timing and dictating when the data stream should be checked, the DAC wouldn't know the difference between the first zero and the second zero.

In the same sense without the LR clock the DAC wouldn't know if the data incoming is for the left or the right channel.

Those three clocks have to be synchronous.

The master clock isn't strictly required to decode any data. Converter chips however, most of the time, require the master clock for the functioning of internal operations, such as digital filters. In a lot of chips the master clock does not have to be synchronous with the other three clocks either, although it usually is, as the other three clocks are usually generated by clock division of the master clock. The master clock can run at many different speeds and ADC/DAC converters specify the limits to which they can work. 256x fs is a nominal figure for the master clock as most ADC/DAC converters can operate from 32khz >192 from it.

The master clock obviously runs the fastest and if you're going to buy an expensive Tentclock/Kwakclock thingymabob, it is to this frequency that you will purchase.

I think that's about it. Someone correct me if I've missed something all these years
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Old 25th February 2011, 04:26 AM   #92
rsdio is offline rsdio  United States
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Originally Posted by 5th element View Post
The Bit clock is the clock used to time and decode the data stream and usually operates at 64x fs. In other words the bit clock is high, check data stream for it's polarity, okay, it's a 0. Bit clock goes low, look again at the data stream, okay its another zero. Without the bit clock doing the timing and dictating when the data stream should be checked, the DAC wouldn't know the difference between the first zero and the second zero.
Overall, I think you did a decent summary. But putting on my pedantic hat, I'd be highly surprised if the Bit Clock is both active high *and* active low. Most likely, it's going to sample the data line on the rising edge *or* the falling edge of the Bit Clock, but not both. DDR memory works on both clock transitions, but most clocked data systems only look for one specific transition.
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Old 25th February 2011, 04:59 AM   #93
SunRa is offline SunRa  Romania
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Thanks for your explanations, much appreciated!

Following from this, it means that the master clocks (for 44Khz and 48Khz domains) on the FPGA board is used to derive the wordclock (or bit clock, that is). The bit clock is then fed to the dac.

The difference is that the ESS 9018 will do ASRC on it while using its own oscillator, while more common DAC architectures, such as AD1955 or AK4396 will rely solely on the data coming from the fpga.

An ideal procedure then, would be to have the two master oscillators on the DAC board, let the DAC derive the bit clock and feed the entire system (fpga, pc, etc). Is this correct?

Last edited by SunRa; 25th February 2011 at 05:05 AM.
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Old 25th February 2011, 05:58 AM   #94
rsdio is offline rsdio  United States
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An ideal procedure then, would be to have the two master oscillators on the DAC board, let the DAC derive the bit clock and feed the entire system (fpga, pc, etc). Is this correct?
Assuming that the DAC board has a better clock circuit, then: yes. But it's entirely possible for the USB-to-I2S board to have a clock that is just as good, in which case neither is ideal. It could easily turn out to be "six of one, half dozen of the other" - i.e. - exactly the same.

As Dan Lavry's white paper explains, there's no way that an external clock can be 'better' than a properly-designed internal clock. Since the ideal design would have the USB-to-I2S board and the DAC board sharing a chassis, a clock on either board would basically be 'internal.'

The only detail this summary overlooks is whatever there would be significant degradation between the two boards due to the I2S connector. If Ayre can make this work with a simple ribbon cable, then I don't see how bad it could be. It would be interesting to know whether Ayre places the master clock on the DAC board or the I2S source board.

In other words, the point I am trying to make here is that internal connections do not invite the same kinds of noise and degradation as external cable interconnects. It's not so easy that you can ignore the problem, because even internal connections can be ruined by careless design, but the potential problems are not nearly as huge for internal connections as they are for external cables.

P.S. One consideration is that if the DAC board has a pair of 44.1x and 48x clocks, then some kind of signaling has to be provided between the I2S board and the DAC board to make the switch between sample rates. This alone could require an entirely separate connection in addition to the I2S interconnect. In other words, it's far simpler to have the USB-to-I2S generate the master clocks, because there is where you have a more generic control communication link. With the DAC board slaving to the incoming I2S signals, nothing more is needed to connect the boards. In contrast, any additional clock control communication between boards could introduce ground loops and digital noise.

These comments are all taken from a fairly high level viewpoint, without considering specific chips.
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Old 25th February 2011, 01:22 PM   #95
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Most likely, it's going to sample the data line on the rising edge *or* the falling edge of the Bit Clock, but not both.
Ah indeed, thank you for connecting the last few dots.
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Old 25th February 2011, 05:18 PM   #96
exa065 is offline exa065  Canada
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Thank you everybody for the excellent contributions to the discussion. I wouldnít have been able to explain some of the points as well as you have.

I would also like to thank you for the overwhelming response on the waiting list - www.exadevices.com. Unfortunately I left many of your emails unanswered; there isnít enough time to write to all of you individually. Your questions will be answered on the website after the release of exaU2I.
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Old 25th February 2011, 08:23 PM   #97
SunRa is offline SunRa  Romania
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@ Moderator

Maybe it would be a good idea to split the posts regarding LightPeak in a different thread? I believe there would be other things to be said there.
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Old 25th February 2011, 10:37 PM   #98
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@ Moderator

Maybe it would be a good idea to split the posts regarding LightPeak in a different thread? I believe there would be other things to be said there.
Done

Light Peak/Thunderbolt, the end of USB/Firewire/HDMi and more?

dave
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Old 26th February 2011, 01:42 PM   #99
SunRa is offline SunRa  Romania
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So, any hint on the release date?

Oh, and because we have discussed about using this interface with ESS9018, did you had the chance of using it with more mundane DAC's? Such as AK, AD, Burr-Brown parts? Any impressions on this? Thanks!
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Old 27th February 2011, 03:05 PM   #100
Bunpei is online now Bunpei  Japan
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Originally Posted by rsdio View Post
Overall, I think you did a decent summary. But putting on my pedantic hat, I'd be highly surprised if the Bit Clock is both active high *and* active low. Most likely, it's going to sample the data line on the rising edge *or* the falling edge of the Bit Clock, but not both.
I'd like to recommend that those who are interested in I2S read this specification document,
http://www.nxp.com/acrobat_download/various/I2SBUS.pdf
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