I have a simple question which I hope someone would be able to clarify for me.
It relates to inductance of pcb traces. Why is inductance of a pcb track such a concern?
I appreciate that it can effect the properties cut off of a filter, I can see issues with inductance and analogue circuits.
What about DC circuits, for example power supply lines and digital singals.
Does the following seem plausible?
Inductance on a power supply line can create noise, as components place demands on the supply the voltage dips, then recovers. This creates a spike because of the collapsing filed, ergo more noise.
Similarly does the above apply to switching signals?
So using low inductance traces minimises noises be spikes etc?
Or am I missing something?
It relates to inductance of pcb traces. Why is inductance of a pcb track such a concern?
I appreciate that it can effect the properties cut off of a filter, I can see issues with inductance and analogue circuits.
What about DC circuits, for example power supply lines and digital singals.
Does the following seem plausible?
Inductance on a power supply line can create noise, as components place demands on the supply the voltage dips, then recovers. This creates a spike because of the collapsing filed, ergo more noise.
Similarly does the above apply to switching signals?
So using low inductance traces minimises noises be spikes etc?
Or am I missing something?
For DC circuits it mostly affects how low a power supply impedance you can present. When using bypass caps, series inductance will reduce or eliminate their effectiveness at high frequencies. Thus the advice to keep the leads short. There's a huge difference in the HF properties of a bypass with zero lead length vs. say 1" of lead length. That's why SMT bypasses are so much better than leaded parts and why radials do better than axial leaded parts. Think of PCB traces as extensions of leads. For analog audio it's not such a big deal, though remember that many devices used for audio (opamps, transistors) have no knowledge that they're being used that way, and continue to have very high bandwidths. Consider the LME opamps. They have gain bandwidth products exceeding 50 MHz and can misbehave if you don't consider that in the PCB layout. IMO, lay things out as needed, then solve HF issues locally with short traces and well designed bypass arrangements; consider ground planes too.
Thanks for the response,
Low impedance psu means more current and less voltage drops on line. Where inductance of traces increases then current to equipment drops as could voltage (In a nutshell)
I get the bypassing and am now a happy bunny. I thought there was another reason that I missed but it seems not!
Thanks.
Low impedance psu means more current and less voltage drops on line. Where inductance of traces increases then current to equipment drops as could voltage (In a nutshell)
I get the bypassing and am now a happy bunny. I thought there was another reason that I missed but it seems not!
Thanks.
Unless you are doing RF or high speed digital (and some very high speed analogue) you tend not to consider the trace inductance during layout. That said most designs these days are 4 layers or upwards so have a ground plane (some times several ground planes, which helps keep inductance down).
As Conrad said the biggest killer is extra inductance of bypass capacitors, always choose the smallest package size for a given value and minimise the loop area between the cap and its relevant power pins. Because of mobile devices one of the most used components is 01005 MLCC capacitors.
01005 case size Ceramic Chip Capacitors - MLCCs
For high speed digital you need to control the trace impedance so have to take all parasitics into consideration this is for signal integrity, an example of this is the humble USB, which should be routed on the PCB with 90 ohms differential (50 single ended) between the d+ and d- signals. DDR memory interfaces are a prime example of this.
As said though for the majority of designs you don't have to worry about inductance, unless the layout is really bad or spider legs style star point ground traces are used (here it is very hard to determine inductance and the lack of ground plane will mean it is often higher than can be achieved with a ground plane.
The attached calculator allows you to work out trace inductance:
Saturn PCB Design - PCB Via Current | PCB Trace Width | Differential Pair Calculator | PCB Impedance
That some basic info, there is much more info available regarding signal integrity and bypassing, if you want any links let us know.
Forgot to say, with todays RF rich environment and noise floating about inadvertently capacitivly coupling sections of circuit together can be more problematic than inductance. Though some designs I lay out have to be immune to EMC to above 18GHz on these designs I have to worry about all parasitics caused by the PCB topology.
As Conrad said the biggest killer is extra inductance of bypass capacitors, always choose the smallest package size for a given value and minimise the loop area between the cap and its relevant power pins. Because of mobile devices one of the most used components is 01005 MLCC capacitors.
01005 case size Ceramic Chip Capacitors - MLCCs
For high speed digital you need to control the trace impedance so have to take all parasitics into consideration this is for signal integrity, an example of this is the humble USB, which should be routed on the PCB with 90 ohms differential (50 single ended) between the d+ and d- signals. DDR memory interfaces are a prime example of this.
As said though for the majority of designs you don't have to worry about inductance, unless the layout is really bad or spider legs style star point ground traces are used (here it is very hard to determine inductance and the lack of ground plane will mean it is often higher than can be achieved with a ground plane.
The attached calculator allows you to work out trace inductance:
Saturn PCB Design - PCB Via Current | PCB Trace Width | Differential Pair Calculator | PCB Impedance
That some basic info, there is much more info available regarding signal integrity and bypassing, if you want any links let us know.
Forgot to say, with todays RF rich environment and noise floating about inadvertently capacitivly coupling sections of circuit together can be more problematic than inductance. Though some designs I lay out have to be immune to EMC to above 18GHz on these designs I have to worry about all parasitics caused by the PCB topology.
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