Current Mirror Explanation Needed.

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Ahh yes, but we know EXACTLY how much goes where. We know that the base current is 1/beta of the collector current. Or, vice versa, Ic = beta* Ib. Assume beta = 100, then Ib = (1/100)*14.4mA and Ic = (99/100)*14.4mA.

Now we connect the second transistor, base to base, emitter to gnd. It has the same Vbe, so the same Ib, so the same Ic...
So whatever you hang off that 2nd collector, the 2nd transistor will try to pull the same Ic through it - there's your current mirror!

jan
 
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does that imply that the Ie=β*Ib not only works right-to-left, but the transistor will try to balance Ie and Ib to satisfy that equation in other cases too?

I don't think a transistor has any concept of left or right - it just 'sees' what's connected to its three terminals. It cannot work different than the way it is supposed to.


is the transistor operating in saturation now?

I don't think so. The Vce is equal to Vbe which is 0.6V. I think the definition of saturation is that Vbc is only a few 10's of mV. But others may know that better.

jan
 
I don't think a transistor has any concept of left or right - it just 'sees' what's connected to its three terminals. It cannot work different than the way it is supposed to.

yes, well... i have two objections. you can ignore them if you deem them inappropriate or just moronic. I need to study more...

it can operate differently (depending on how you define "operate", i might be getting a bit boring or infuriating, please don't ban me) if it gets damaged...

second, and this is my main point, i do not know if i am conveying my thoughts properly:

i know if you stick a Ib, it will try to draw the appropriate Ie, but does the transistor try to balance the equation even if you stick a Ie and let Ib be variable?

maybe i have taken the "water valve" parallel a bit too seriously... because a valve sets the water flow, but the water flow can't set the valve position, which the transistor can.

I don't think so. The Vce is equal to Vbe which is 0.6V. I think the definition of saturation is that Vbc is only a few 10's of mV. But others may know that better.

jan

okay. still, you and the rest of the gang have been of great help.
 
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[snip]i know if you stick a Ib, it will try to draw the appropriate Ie, but does the transistor try to balance the equation even if you stick a Ie and let Ib be variable?

Well whatever you 'stick' as Ie needs an Ib to flow, right? For instance, if you ground the base and pull the emitter negative, the emittor will become negative until Vbe becomes 0.6V, then Ie will start to flow. In fact, Ie will increase so much that the current will develop enough voltage across whatever is pulling it negative so that the emitter will not drop any further. You can break the transistor that way, or it can go into heavy saturation, but the behaviour is exactly predictable by the way a transistor 'normally' works.

Now as you hinted, if the transistor gets into saturation, the nice Ic/Ib=beta breaks down. For instance, if you send 1A into the base there's no way that Ic becomes 100A (unless you have a really big one). But for 'normal' use the beta-concept works pretty well.

jan
 
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you're not supposed to know β accurately, anyway... just that it's some large number... at least that's what i've learned from horowitz&hill.

Exactly. Not only does the beta vary between transistors, even the same type, but the Vbe necessary for a specific current also varies.
If you read some of the earlier posts, someone mentioned using smallish (10-100) ohms emitter resistors in both mirror transistors. The resistors provide negative feedback and that will tend to cancel out beta- and Vbe differences.

How does that work? Suppose the 2nd transistor has more beta than the first one. That would give it more Ic than the first one and the 'mirror' is no longer 1:1. But the larger Ic (and Ie) also means that there is more voltage generated across that 2nd transistor Re. That extra voltage can only mean that the Vbe gets a bit smaller, which decreases the Ic/Ie. So it works to diminish the effect of any beta differences (and similarly any Vbe mismatches).

jan
 
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