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Old 24th June 2012, 12:54 PM   #21
DF96 is offline DF96  England
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Quote:
Originally Posted by neoinc
To choose the correct capacitor for a given requirement, can i safely use the formula 2*pi*F*C to find the cutoff freqency i want to decouple? It should acts a like a low pass filter to filter away the high frequency.
1/(2 pi f C) gives you the reactance of the capacitor at a particular frequency. You need to ensure this is much lower than the typical impedances of your circuit. You can do a very rough estimate by considering the supply voltage and current for the stage. Bear in mind that circuits often have to be well-behaved at frequencies far removed from the actual operation frequency e.g. audio has to be stable from well below 1Hz (speech syllabic rate, music phrasing) up to many MHz or more (to cope with RF interference and loop stability).

Quote:
Originally Posted by Overdream
Dont think to much, just give me your opinion and done....
And read my question carefully, did i asked how to fish ?? No !! I asked what is best caps ( for you )
Sorry, I usually find thinking to be preferable to being clueless due to lack of thought. The best caps for me would depend on what I was doing: phono preamp or RF transmitter?
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Old 25th June 2012, 01:40 PM   #22
marce is offline marce  United Kingdom
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Have a read of this thread:
paralleling film caps with electrolytic caps

Better still google bypass/decoupling capacitors, there is a shed load of info regarding it as it is a big and important part of digital design.
That important I am currently on a 4 day course in Munich on Power supply integrity, where we will cover de-couplers or bypass capacitors.

Generaly if you are using 2 or 3 low value ceramics use low Q X7R near the device pins (as close as possible). For crystals and osc's tend to use a single low value COG, you get better EMC performance. Sprinkle higher value reservoir caps areound the board, 10uf ceramic here and there, and a couple of highish value electrolytics (100+ uH). For the low value, small packages are best (0402) as close to the pins as possible to reduce inductance of any leads. For digital a ground plane is realy mandatory these days due to signal rise times...
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Old 25th June 2012, 01:54 PM   #23
marce is offline marce  United Kingdom
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In fact today with the high frequency noise all around us, SMPS supplies, high speed logic , fast rise times etc the right choice of decoupling (or bypass) capacitors can make or break a design, especially if you do commercial designs and have to have the designs pass EMC testing (though this is just important for DIY design, for ultimatre fidelity).
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Old 28th June 2012, 10:28 AM   #24
marce is offline marce  United Kingdom
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DF96, some interesting thing coming out of this Power Integrity Analysis software course, the main one being that decoupling caps are pretty usless for high speed designs, and are not much use at lower speed digital designs, especialy the standard 100nF decoupler lover by engineers throughout the world. And through hole caps are a total waste of time for digital decoupling.
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Old 28th June 2012, 11:18 AM   #25
DF96 is offline DF96  England
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I guess it depends on speed. 30 years ago a 100nF through-hole decoupler per chip was just about good enough for 20MHz TTL. Then along came MOS memory and ground-bounce and it all got complicated. Sadly, this seemed to coincide with a decline of interest in RF and analogue design by many EEs and their tutors - they thought that 'digital' had done away with such old-fashioned things. Now we have GHz logic and RF sitting next to each other in everyone's pocket. We now have to teach RF again, but we call it EMC?

So you do your excellent design, then the Chinese factory saves a few pence by omitting a few components here and there. After all, how many people actually do batch checks for EMC performance?
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Old 28th June 2012, 12:54 PM   #26
marce is offline marce  United Kingdom
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I will comment more on the course and the software I am playing with, but it should brighten your day to know I am suffering S and Z parameter calculations etc. Of course I have 16Ks worth of software to do the hard work for me.
The SMD 100nF are coming in at around 12MHz resonance, 3V3 and 1V5 on an Intel Atom board, with plane impedances varying greatly over the frequecy range. It is nice to have plots to see the distribution, and allows us to to tailor the capacitor distribution and values to achieve the lowest possible impedance at the supply pins for the operating frequecies of the devices.
Neoinc, this is important for EMC as the higher the impedance at target frequecies will cause voltage drops and will increase overall noise, decoupling especialy for digital is not just throwing a few caps down based on myths and rules of thumb.

Last edited by marce; 28th June 2012 at 01:05 PM.
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Old 28th June 2012, 01:23 PM   #27
neoinc is offline neoinc  Singapore
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Marce, thanks for the sharing. EMC is a very black art indeed.
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