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Old 16th August 2009, 01:24 PM   #1
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Default Discrete ring counter

Hello!

I am searching for a semi standard circuit. I want to make this logic function with a high speed discrete circuit:

Click the image to open in full size.

There are some important key factors to this:
- The sequence must be fail proof. I.E. the out 1-3 and the out 4-6 must allways be in sync.
- The timing is crucial. The pulses 1-3 and the pulses 4-6 must be identical. If the width of the pulses 1-3 is identical to the positive input pulses, the pulses 4-6 must be identical to the negative input pulses.
- The resolution must be at least 100ns.
- The delay must be less than 50ns.
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Old 16th August 2009, 02:08 PM   #2
MaxS is offline MaxS  France
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Hello,



For the moment, a quick search gave me this :
http://www.vk2zay.net/article/file/938
I'll run the sim later.


MaxS
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Old 16th August 2009, 02:29 PM   #3
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Thanks MaxS

I found that one too. I found out that the logic is ok, but the curve shapes are not that good.
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Old 16th August 2009, 02:57 PM   #4
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Does anyone have an idea why this does not work?
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Old 16th August 2009, 04:36 PM   #5
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Quote:
Originally posted by Snickers-is
Does anyone have an idea why this does not work?

Yes. /SET and /RST inputs on a '74 are inverting inputs and your
reset signal in is holding all the flipflops in the init state. Try inverting
the reset signal, i.e. hold it normally high and pulse it low to reset the
counter.

Your output waveform will switch at 1/2 the frequency you expect.
Can you double the clock? Is it a free-running clock or something
from an encoder?

Can you reveal a little more about the use? Why are you depending
on exactly co-incident edges? There is probably a simpler way to
solve the problem w/o high speed logic...

Michael
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Old 16th August 2009, 06:36 PM   #6
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Thanks Michael! That solved it, mostly.

I do not want to go too deeply into what this is for.

The logic function is crucial, but it does not have to be done with logic circuits. It can be done with a programmable controller or with transistors too.

Here is another attempt that worked out better, but it behaves a bit strange before it has been reset:
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Old 17th August 2009, 11:07 AM   #7
MaxS is offline MaxS  France
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Hello Sirs,



If your application allows you CPLD design, you could design it as a state machine.
I will try if it is possible to simply describe it.



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Old 17th August 2009, 11:41 PM   #8
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Hello MaxS

What is CPLD? A processor of some kind?
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