Unless its a ladder DAC. . . I have an HP 5370A with upgraded input and processor but its resolution is still really an order of magnitude too high. I don't think that is a path to useful info.
The PLL is also limited by both the PLL and the residual of the VCO (VCXO). To get good info on the phase noise of a Crystek or an NDK you really need a much more sophisticated solution, most likely one with cross correlation. Given that those are available for $30-$40 now it may be easier to just use one. When the phase noise is below a certain level its lost in the intrinsic noise and resolution of the DAC/ADC.
Here are some references for those who want to understand the jargon (I know John is up on this):
http://www.ieee-uffc.org/frequency-control/learning/pdf/Nelson-Phase_Noise_Measurements.pdf
http://www.keysight.com/upload/cmc_upload/All/PhaseNoise_webcast_19Jul12.pdf?&cc=US&lc=eng
Low-Cost Phase Noise Measurement |
Murry,
Please forgive the delay, Thank you very much for the Scan of the Application note
Food for thought on the "comparative" Jitter analyser...
The unit I purchased is however the "PLL" type mentioned in the paper as "Ill suited to measurements of LF Phase noise" - well this design sure will be with the chosen capacitors used in the Integrator (and the input base current of the integrator Opamp)...
Please forgive the delay, Thank you very much for the Scan of the Application note
Food for thought on the "comparative" Jitter analyser...
The unit I purchased is however the "PLL" type mentioned in the paper as "Ill suited to measurements of LF Phase noise" - well this design sure will be with the chosen capacitors used in the Integrator (and the input base current of the integrator Opamp)...
that would be excellent, waiting for your progress even if I know you're busy with other stuff
Is this question still active.... sorry found this thread by accident.
I have the same analyzer, got it fro Ultra Analog when I did design work for them some 20 years ago.
It is a great device, I have the schematic somewhere (only on paper) and a schematic of the probe as well.
Cheers
I've got the unit sitting on top of a rack behind me - not had not much time to look at it, but I'd very much like to investigate the possibility of designing an affordable / DIY jitter analyzer for audio use.
I had a quick peak inside, but worried a bit when the probe interface which at first appears balanced, is in fact not.
The jitter detection Edge is chosen via an XOR (selected via the front panel edge switch).
I'd really appreciate the schematics, it might restart the project and I'd be happy to update the design for DIY users
DIY developers would really benefit from an affordable Jitter analyzer
I've got the unit sitting on top of a rack behind me - not had not much time to look at it, but I'd very much like to investigate the possibility of designing an affordable / DIY jitter analyzer for audio use.
I had a quick peak inside, but worried a bit when the probe interface which at first appears balanced, is in fact not.
The jitter detection Edge is chosen via an XOR (selected via the front panel edge switch).
I'd really appreciate the schematics, it might restart the project and I'd be happy to update the design for DIY users
DIY developers would really benefit from an affordable Jitter analyzer
I have seen some Jitter Tool tests by the AP555 and looks as BS. Also only related using the SPDIF signal source and given result.
Also to provide for DIY users, this is a dream while it matters on HW & SW.
May read on the TI pdf, indicates that some jitter inherited to the DAC have to be done with additional signal injection to the clock.
https://training.ti.com/sites/default/files/docs/TIPL%204703%20-%20Understanding%20Signal%20to%20Noise%20Ratio%20and%20Noise%20Spectral%20Density%20in%20High%20Speed%20Datat%20Converters_3.pdf
hp
I've got the unit sitting on top of a rack behind me - not had not much time to look at it, but I'd very much like to investigate the possibility of designing an affordable / DIY jitter analyzer for audio use.
I had a quick peak inside, but worried a bit when the probe interface which at first appears balanced, is in fact not.
The jitter detection Edge is chosen via an XOR (selected via the front panel edge switch).
I'd really appreciate the schematics, it might restart the project and I'd be happy to update the design for DIY users
DIY developers would really benefit from an affordable Jitter analyzer
Hi JohnW,
I can send you the schematics I have, but I don't think it is a DIY project.
Even though the schematic is not too complicated the layout and execution is quite important here. I also found a copy of a FAX "!" i received of the probe schematic.
I will fire up the unit soon, to check if it still works.
Send me a PM for your details
Peter
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