SAR ADC for high performance audio ADC project [LTC2380-24] - Page 14 - diyAudio
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Old 12th June 2017, 07:00 PM   #131
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Quote:
Originally Posted by xx3stksm View Post
Hi, I found this site recently.This is the very concern thing I want to know.I made ADC to digitalize a record one years ago.
I prefer SAR to delta-sigma because I couldn't get good result from pcm4202 before and my DAC use multibit DAC chips.I chose AD7982. This is the PCB.It works well for digitizing.
Very nice. How did you solder the Artix 7? Did you use a reflow oven, or hot air/IR?
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Old 13th June 2017, 04:57 AM   #132
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Quote:
Originally Posted by chris719 View Post
Very nice. How did you solder the Artix 7? Did you use a reflow oven, or hot air/IR?

BGA is annoyance for self-making. I usually don't use this type of package because I can't solder by myself.I had no choice about this PCB to use BGA because I need somewhat large memory(512kbytes).

There is a PCB manufactures who arrange assembly including BGA soldering.It needs metalmask whose cost is almost same as PCB.In this case,both are probably US$450(PCB cost include 5pcs PCB,metalmask cost includes 4pcs BGA soldering fee).

If PCB doesn't have BGA,total cost is half.BGA is annoyance indeed.
One merit of BGA is reliability.BGA soldering is ckecked with X-ray.QFP soldered by myself sometimes has contact failurs.I don't know the merit is worthy of cost.
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Old 17th June 2017, 01:28 PM   #133
Frex is offline Frex  France
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Post News...

Hello,

xx3stksm , you have also made a good job !
Your screen-shoots seem to show analysis software, does it is from you (for your board)
or is that a commercial one ? It looks pretty well.


Now, some news of the project.

After receiving the SDRwidget bare PCB, I populated the board and uploaded the firmware
on it without major issue. Anyway, that require some reading that take some time.

To test the USB/I2S link that provide the USBwidget board, i used a small CPLD board
that emulate the I2S like an ADC and provide also the master clock.
The data sent by this board is a 48points sine lockup-table with selectable amplitude of -1dBFS or -80dBFS.

And, the SDR widget works really well !
I used it on Ubuntu at any sampling rate without any driver (plug and play ).
I run it with jaaa FFT software in full duplex mode at 192kHz successfully.

On windows (win7-64), in UAC1 mode all win applications recognize it at 48k/24bits.
When ASIO drivers are installed on windows, 96/192kHz operation are possible
but the application must be able to use ASIO.
I tried Arta and REW 5.1 and both work with ASIO at any sampling rate.
So, I am very enthusiast with it !

You can show below a small picture of the test setup (SDR board and CPLD test) :

Click the image to open in full size.


Of course, the next step now is to connect the SDR widget to my ADC for replacing
the SPDIF link and the PCI sound card.
Compared to any others solution (like XMOS), for up to 192k operation
the SDRwidget is very interesting solution, with overall price much lower
and the open sourced project is very DIY friendly ! (much infos about it on Google).

Regards.

Frex


(Note that i have some SDRwidget bare PCB available, if you need to get one, go HERE.)
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Old 17th June 2017, 10:10 PM   #134
1audio is offline 1audio  United States
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The latest Win 10 creators update is supposed to have native UAC 2 drivers and may work without ASIO (or a hacked Thesycon driver) like Linux.

Sent from my LG-H811 using Tapatalk
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Old 19th June 2017, 01:29 PM   #135
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Quote:
Originally Posted by Frex View Post
Hello,

xx3stksm , you have also made a good job !
Your screen-shoots seem to show analysis software, does it is from you (for your board)
or is that a commercial one ? It looks pretty well.
I use RX4(iZotope) for audio analysis.It is mainly for editting audio signal to controll declic,denoise,equalizer and sampling conversion.I used this for the first time to degitalizing of my records.Then I found this was also good tool for analysis.

By the way I read your measurement data at #56.You got -115.1dBFS noise level at 48kHz/s.That's great.My ADC board as I posted at #130 was -111.2dB.This was sampled at 768kHz.If it was sampled like you(1.5MHz),it can gain 3dB,total noise floor -114.2dB.

I think this doesn't depend on a chip used.Your data is almost close to physical limit.My board still has some problems.After fixing them,mine probably becomes close to you.My goal is -120dB.From your data and another consideration,the key to reach -120dB is high sampling rate(6MHz)and carefull board layout.I think it's possible.
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Old 19th June 2017, 05:00 PM   #136
Frex is offline Frex  France
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Thank you for the tip Demian.
I read a little and that seem only work for playback, at least for now.
Anyway, i try to update my win10 to latest creator update to try this, i'm curious...


Hello xx3stksm,
Too bad that izotope price list is so high, that seem a good tool.

What do you use as processing in the FPGA ? Decimating FIR as me ?
Note that i don't know what clock you have used, but low phase noise and short path
is essential to meet the full ADC specs.
Regards.


Frex
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Old 20th June 2017, 06:45 AM   #137
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Quote:
Originally Posted by Frex View Post
What do you use as processing in the FPGA ? Decimating FIR as me ?
Note that i don't know what clock you have used, but low phase noise and short path
is essential to meet the full ADC specs.
Regards.
Frex
The processing in FPGA is plain FIR(40kHz cutoff,1024 order). It has sharp cutoff to eliminate spectrums which have potential chance to be aliasing noise.
SAR.jpg

High sample rate SARs like LTC2380 have internal clock for its conversion. External clock into the chip acts only for shift clock of sampled data acording to datasheet.
I think stable power and analog signal layout are more important than external clock.
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