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|9th May 2012, 05:25 PM||#1|
Join Date: Dec 2004
Jitter measurement using ASRC?!
ASRC is "de-jitterizer" for DAC ICs. It makes DACs work synchronous to some good clock nearby.
What ASRCs don't do is eliminate input jitter.
ASRCs are a kind of digital system which literally represent DAC and ADC combo, where DAC and ADC have different clock domains.
Let's say the internal DAC gets jitter from I2S input. It's waveform gets shaped with that jitter.
Then internal "ADC" samples the waveform at precise time periods driven by precise clock, and sends it to I2S output.
Therefore, we've got 24bit jitter analyzer for i2s.
To see what's going on, we'd use popular J-Test signal as we use in regular DAC-ADC jig.
Which ASRC would suit the rig? It should be old to not use kind of PLL/averaging on inputs, but have good/precise math engine to have good sampling precision.
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