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Old 1st October 2012, 05:49 PM   #561
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Quote:
Originally Posted by jackinnj View Post
It's not instantaneous -- and your averaging capacitor may too large. Try running the sim with an o'scope and watch the buf output increase to the RMS value.
Thanks.

OK, well, I have tried and tried to get the scope to work in Tina and it just won't. I don't know what I'm doing wrong and I've read the help section on it.

I used 1uF for Cav from the data sheet for the chip.
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Old 1st October 2012, 06:06 PM   #562
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MSIM doesn't have the AD637, so I created it from Analog's website -- using the post filter -- the green trace is the DC value of the RMS voltage:

Click the image to open in full size.
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Old 1st October 2012, 06:20 PM   #563
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Thank you! I used the spice model from the Analog website and imported it into Tina.

So, 70ms to settle @ 1kHz. Is that good or bad?
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Old 1st October 2012, 07:04 PM   #564
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70 ms to settle @ 1 kHz. Is that good or bad?
You tell us--how much ripple (i.e. distortion) and what oscillator settling time can you accept? When designing something like this you need a clear goal, or you'll be running in circles.

Also don't try to re-invent the wheel; if you need both fast settling at the lowest frequencies and very low distortion, a sample-and-hold based level detector (as used in essentially any newer commercial generator) is probably the by far best solution. Not easy to design though (I'm currently testing my 3rd generation circuit, and I'll need a 4th revision to get where I want).

Simpler to handle is the sin^2 + cos^2 approach. Wire-up two multipliers as square functions, and feed them from the lowpass/bandpass output of the SV filter. The sum of their outputs gives a theoretically ripple-free and instantaneous level detector. Practice will show you several limitations, but still the result is probably more usable than a simple rectifier or RMS-DC converter.

Samuel
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Old 1st October 2012, 07:22 PM   #565
davada is offline davada  Canada
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Quote:
Originally Posted by Samuel Groner View Post

Simpler to handle is the sin^2 + cos^2 approach. Wire-up two multipliers as square functions, and feed them from the lowpass/bandpass output of the SV filter. The sum of their outputs gives a theoretically ripple-free and instantaneous level detector. Practice will show you several limitations, but still the result is probably more usable than a simple rectifier or RMS-DC converter.

Samuel
Hi Samuel,

You darn near need an AGC just to keep these two (sin^2 + cos^2) equal amplitude to avoid ripple.

How are you managing the pedestal error, glitches and ringing with the THSH?

I'm getting very frustrated.

Cheers,
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Old 2nd October 2012, 02:03 AM   #566
benb is offline benb  United States
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Quote:
Originally Posted by Samuel Groner View Post
You tell us--how much ripple (i.e. distortion) and what oscillator settling time can you accept? When designing something like this you need a clear goal, or you'll be running in circles.

Also don't try to re-invent the wheel; if you need both fast settling at the lowest frequencies and very low distortion, a sample-and-hold based level detector (as used in essentially any newer commercial generator) is probably the by far best solution. Not easy to design though (I'm currently testing my 3rd generation circuit, and I'll need a 4th revision to get where I want).

Simpler to handle is the sin^2 + cos^2 approach. Wire-up two multipliers as square functions, and feed them from the lowpass/bandpass output of the SV filter. The sum of their outputs gives a theoretically ripple-free and instantaneous level detector. Practice will show you several limitations, but still the result is probably more usable than a simple rectifier or RMS-DC converter.

Samuel
I've been thinking about this ever since the 20Hz oscillator with really long settling time was mentioned, post #218 and probably before. The sine squared plus cosine squared idea is the analog function I was trying to imagine how to do, but it does give a continuous level output instead of sampled or peak-detected, and with an appropriate loop filter should result in a much faster settling time.

I've been thinking (speaking of reinventing the wheel) of using a microcontroller with an A/D converter reading the output and comparing it with an internally generated sine of the same frequency and phase, at 100 or 1,000 points per sample. This would also give (near) continuous level detection (at and near zero crossing the ratio of the two may not be accurate enough to use), using a D/A converter to directly drive the gain element, and both the signal level detect and loop filtering could be done completely in software.

One problem I don't recall seeing mentioned with the CDS cell is its own response time which becomes part of the loop filtering - and its resistance responds MUCH faster to an increase in light than to a decrease in light, likely complicating things (what's more, it even has a memory effect, similar to dissipation factor or "soakage" in capacitors). This is only a "moderate" problem at higher frequencies, but at 20 Hz the response may be fast enough to cause distortion unless the loop filter has a substantially lower cutoff frequency.
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Old 2nd October 2012, 02:28 AM   #567
davada is offline davada  Canada
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[QUOTE=benb;3186932]

I've been thinking (speaking of reinventing the wheel) of using a microcontroller with an A/D converter reading the output and comparing it with an internally generated sine of the same frequency and phase, at 100 or 1,000 points per sample. This would also give (near) continuous level detection (at and near zero crossing the ratio of the two may not be accurate enough to use), using a D/A converter to directly drive the gain element, and both the signal level detect and loop filtering could be done completely in software.

Hi benb,

I tried something similar to this with much less demanding sampling at one sample per cycle. What I found is small embedded processors can't keep up to real time events even though they run thousands of times faster. At low frequencies it was not such a problem but as the frequency increased... This was with bear bone code. Although I was trying to do this using the built in SPI running at 12MHz. The processor was running at 48MHz.

I'm still entertaining the idea of using a processor but for lesser demanding tasks. It is doable if most of the real time events are handled outside the processor with discrete hardware. I'm sure one could move up to more a powerful processor and have some success but in interest of keeping the cost down....
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Old 2nd October 2012, 08:56 AM   #568
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Quote:
You darn near need an AGC just to keep these two (sin^2 + cos^2) equal amplitude to avoid ripple.
Yes, that's the main problem--the time constants of the integrators will need to be reasonably well matched.

Quote:
How are you managing the pedestal error, glitches and ringing with the THSH?
I can't reduce them to zero either, but 100 uVrms fundamental frequency content should be feasible with modest circuit complexity. Most of the ripple energy tends to be located at high multiples of the fundamental frequency, and thus is very effectively low-pass filtered by the state-variable topology. If you drop me an e-mail with your schematic and detailed results I might be able to offer more specific help.

Quote:
I've been thinking (speaking of reinventing the wheel) of using a microcontroller with an A/D converter reading the output and comparing it with an internally generated sine of the same frequency and phase, at 100 or 1,000 points per sample. This would also give (near) continuous level detection (at and near zero crossing the ratio of the two may not be accurate enough to use), using a D/A converter to directly drive the gain element, and both the signal level detect and loop filtering could be done completely in software.
Quote:
I tried something similar to this with much less demanding sampling at one sample per cycle. What I found is small embedded processors can't keep up to real time events even though they run thousands of times faster. At low frequencies it was not such a problem but as the frequency increased...
I've contemplated this as well, but have not done any practical work yet. I think the most promising path would be to implement a first stage in the analog domain (peak detector or track-and-hold), then implement the second stage and integrator with AD and DSP. Surely one'd use an MDAC for the multiplier element.

Just for the records, much has been said here already:

My implementation of the Cordell Distortion Analyser

Samuel
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Old 2nd October 2012, 02:36 PM   #569
davada is offline davada  Canada
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Quote:
Originally Posted by Samuel Groner View Post
Yes, that's the main problem--the time constants of the integrators will need to be reasonably well matched.



I can't reduce them to zero either, but 100 uVrms fundamental frequency content should be feasible with modest circuit complexity. Most of the ripple energy tends to be located at high multiples of the fundamental frequency, and thus is very effectively low-pass filtered by the state-variable topology. If you drop me an e-mail with your schematic and detailed results I might be able to offer more specific help.

I had to try everything simpler first with discrete circuits and am now just moving on to what I proposed to you earlier this year. I'll let you know how it goes.




I've contemplated this as well, but have not done any practical work yet. I think the most promising path would be to implement a first stage in the analog domain (peak detector or track-and-hold), then implement the second stage and integrator with AD and DSP. Surely one'd use an MDAC for the multiplier element.

Just for the records, much has been said here already:

My implementation of the Cordell Distortion Analyser

Samuel
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Old 2nd October 2012, 03:09 PM   #570
davada is offline davada  Canada
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Quote:
Originally Posted by Samuel Groner View Post
Yes, that's the main problem--the time constants of the integrators will need to be reasonably well matched.



I can't reduce them to zero either, but 100 uVrms fundamental frequency content should be feasible with modest circuit complexity. Most of the ripple energy tends to be located at high multiples of the fundamental frequency, and thus is very effectively low-pass filtered by the state-variable topology. If you drop me an e-mail with your schematic and detailed results I might be able to offer more specific help.





I've contemplated this as well, but have not done any practical work yet. I think the most promising path would be to implement a first stage in the analog domain (peak detector or track-and-hold), then implement the second stage and integrator with AD and DSP. Surely one'd use an MDAC for the multiplier element.

Just for the records, much has been said here already:

My implementation of the Cordell Distortion Analyser

Samuel
I'll try this again now that I'm more awake.

I had to try everything simpler first with discrete circuits and am now just moving on to what I proposed to you earlier this year. I'll let you know how it goes.

" I've contemplated this as well, but have not done any practical work yet. I think the most promising path would be to implement a first stage in the analog domain (peak detector or track-and-hold), then implement the second stage and integrator with AD and DSP. Surely one'd use an MDAC for the multiplier element."

We think alike with this.
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