Low-distortion Audio-range Oscillator

An idea I've been pondering for some time is the use of state-variable oscillator topologies with higher order than the usual second. Such offer improved rejection of distortion from the leveling loop. One of the very few resources on higher-order state-variable filters is this one: linriley.pdf‎

Here is an adaptation as 4th-order oscillator: 4th-order_state-variable_oscillator_r1.pdf

This is just a proof of concept, without any optimization. Simulated settling time is ~150 ms after startup.

For a tunable oscillator the extra cost of switching the feedback network of more integrators is probably higher than that of a better leveling loop, but for a fixed frequency "reference" design, or "cost no object" DIY, it might be worth considering.

Samuel

Hi Samuel,

This may seem like a dumb question, but for about the same complexity, especially in tuning, how would this compare to just cleaning up the output of the traditional second order SVO with a subsequent second order SV bandpass?

I'm guessing the concern might be the precision of the frequency tracking of the BPF to the SVO, that matter being somewhat dependent on the Q of the BPF. A slight frequency mis-tracking would cause an amplitude error that would be worse for a high-Q BPF. However, a very strongly filtered clean-up agc could be added that monitors the amplitude output of the BPF and adjusts the amplitude setting of the SVO agc in accordance. The advantage here is that the added agc loop does not suffer the kind of loop stability issues that are seen in an SVO agc loop.

If someone was really crazy, they could add a frequency tweak control loop that adjusted the SVO frequency ever so slightly to be right at the center of the subsequent BPF. The cleanup SV BPF could then be made very sharp. This sort of architecture and circuitry would be very similar to the auto-tune circuit in a THD analyzer.

Cheers,
Bob
 
The notes in the AP SYS1 claim the second stage tuning of the notch filter is far less sensitive than the first and only the first stage requires fine tuning.
I wonder if the same would hold true for an SVO. The second stage doesn't necessarily has to have such a high Q and exact tuning may not be critical.
 
An idea I've been pondering for some time is the use of state-variable oscillator topologies with higher order than the usual second. Such offer improved rejection of distortion from the leveling loop. One of the very few resources on higher-order state-variable filters is this one: linriley.pdf‎

Here is an adaptation as 4th-order oscillator: 4th-order_state-variable_oscillator_r1.pdf

This is just a proof of concept, without any optimization. Simulated settling time is ~150 ms after startup.

For a tunable oscillator the extra cost of switching the feedback network of more integrators is probably higher than that of a better leveling loop, but for a fixed frequency "reference" design, or "cost no object" DIY, it might be worth considering.

Samuel

Samuel this link isn't working linriley.pdf‎. Is the server down?

Never mind I found it.
 
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This may seem like a dumb question, but for about the same complexity, especially in tuning, how would this compare to just cleaning up the output of the traditional second order SVO with a subsequent second order SV bandpass?

I'm guessing the concern might be the precision of the frequency tracking of the BPF to the SVO, that matter being somewhat dependent on the Q of the BPF. A slight frequency mis-tracking would cause an amplitude error that would be worse for a high-Q BPF. However, a very strongly filtered clean-up agc could be added that monitors the amplitude output of the BPF and adjusts the amplitude setting of the SVO agc in accordance. The advantage here is that the added agc loop does not suffer the kind of loop stability issues that are seen in an SVO agc loop.

If someone was really crazy, they could add a frequency tweak control loop that adjusted the SVO frequency ever so slightly to be right at the center of the subsequent BPF. The cleanup SV BPF could then be made very sharp. This sort of architecture and circuitry would be very similar to the auto-tune circuit in a THD analyzer.

I think the noise of the 4th-order oscillator (if it can be made to work in practice) will be lower than that of a 2nd-order oscillator followed by a 2nd-order low-pass filter, everything else equal. As you note amplitude flatness will suffer, and I'm not sure if the addition of a second leveling loop is as easy as you say--it will need to settle fast as well. I've briefly looked into a setup (2nd-order oscillator followed by 2nd-order low-pass filter) where the leveling loop senses the amplitude at the output of the low-pass filter, and this seems to introduce additional difficulties (I don't recall if I ended up with a working circuit).

IMHO, placing the filter at the multiplier output is more promising. The signal level at this node is very low (nominally zero), so it will be easy to design the filter with low distortion contribution. I've simulated this some time ago, and IIRC the filter needs to be a bandpass.

Samuel
 
An idea I've been pondering for some time is the use of state-variable oscillator topologies with higher order than the usual second. Such offer improved rejection of distortion from the leveling loop. One of the very few resources on higher-order state-variable filters is this one: linriley.pdf‎

Here is an adaptation as 4th-order oscillator: 4th-order_state-variable_oscillator_r1.pdf

This is just a proof of concept, without any optimization. Simulated settling time is ~150 ms after startup.

For a tunable oscillator the extra cost of switching the feedback network of more integrators is probably higher than that of a better leveling loop, but for a fixed frequency "reference" design, or "cost no object" DIY, it might be worth considering.

Samuel

I don't get a forth order response from this at any output. The slope is 12dB/oct at best. The BPb output is a duplicate of the LP output with nearly an identical phase.
 
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The added noise contribution of a second stage is a good point. Extreame amplitude flatness isnt a high priority - IMO.
Why not do both -- run the 4th order output and use a BPF also. So its a little more complex. But wow what results it would produce!

Thx-RNMarsh
 
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Have you run a Monte Carlo sim, to see how close matched the C's and R's has to be? I've looked into something similar and found that close matching was essential.

The Q is indeed sensitive to integrator time constant matching, and certain other passives (that's not the case for the classic 2nd order state-variable oscillator). However, this does not prevent proper operation as long as the multiplier has sufficient authority. For the shown circuit, a Monte Carlo simulation with 5% Cs and 1% Rs suggested that the authority of the multiplier is sufficient, although not with much margin. For a practical implementation one could make R5 variable (+-10% should be enough), which seems to be a complete cure. Other than this, I've not been able to find any issue with the topology so far.

I don't get a forth order response from this at any output. The slope is 12 dB/oct at best.

That's what I see: 4th-order_state-variable_oscillator_r1_freq_response.pdf

Note that the leveling loop should be disabled for AC analysis. As input I'm using a 1m current source injected into the inverting input of U5.

Samuel
 
The Q is indeed sensitive to integrator time constant matching, and certain other passives (that's not the case for the classic 2nd order state-variable oscillator). However, this does not prevent proper operation as long as the multiplier has sufficient authority. For the shown circuit, a Monte Carlo simulation with 5% Cs and 1% Rs suggested that the authority of the multiplier is sufficient, although not with much margin. For a practical implementation one could make R5 variable (+-10% should be enough), which seems to be a complete cure. Other than this, I've not been able to find any issue with the topology so far.



That's what I see: 4th-order_state-variable_oscillator_r1_freq_response.pdf

Note that the leveling loop should be disabled for AC analysis. As input I'm using a 1m current source injected into the inverting input of U5.

Samuel

Can you post your spice file for this?
 
What am I doing wrong here?

Doesn't matter whether I use a current source or voltage source this is what I get.
 

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Here is an adaptation as 4th-order oscillator: 4th-order_state-variable_oscillator_r1.pdf
Far be it from me to critique the astute electronics designers in this thread, but ...

I wonder about those four diodes whose only load is the positive input of an opamp wired as a buffer. The voltage at that node relies on lots of "unknowns" as far as someone reading the schematic (though the simulator surely has values for them) - the opamp's input current, the reverse current of the diodes (rather temperature dependent), the stray capacitance,... and it's impossible to guess how these are going to interact.

What does the output of U6 look like? Does it change much if you connect a resistor (maybe 100k to 1meg) from the positive input of U6 to ground or to V-? I'd put a resistor or current source there, scaled to overcome these other things, just out of principle.
 
Far be it from me to critique the astute electronics designers in this thread, but ...

I wonder about those four diodes whose only load is the positive input of an opamp wired as a buffer. The voltage at that node relies on lots of "unknowns" as far as someone reading the schematic (though the simulator surely has values for them) - the opamp's input current, the reverse current of the diodes (rather temperature dependent), the stray capacitance,... and it's impossible to guess how these are going to interact.

What does the output of U6 look like? Does it change much if you connect a resistor (maybe 100k to 1meg) from the positive input of U6 to ground or to V-? I'd put a resistor or current source there, scaled to overcome these other things, just out of principle.

I think the sim is just demonstrating a principal and is not a design.
It serves to show the settling time and loop stability.
 
I wonder about those four diodes whose only load is the positive input of an opamp wired as a buffer. The voltage at that node relies on lots of "unknowns" as far as someone reading the schematic (though the simulator surely has values for them) - the opamp's input current, the reverse current of the diodes (rather temperature dependent), the stray capacitance,... and it's impossible to guess how these are going to interact.

What does the output of U6 look like? Does it change much if you connect a resistor (maybe 100k to 1meg) from the positive input of U6 to ground or to V-? I'd put a resistor or current source there, scaled to overcome these other things, just out of principle.

The voltage at the diode summing node is actually not that ill-defined as it looks at first--one of the diodes is always forward-biased, becomes relatively low impedance and delivers the current for the reverse-leakage of the other three. The only problem occurs when the opamp input sources more current than the sum of the reverse-leakage of the diodes. The typical leakage of a 1N4148 is around 10 nA at room temperature and for a few volts reverse-bias. So if U6 becomes a FET input (e.g. a TL072 together with U7), we should be safe even with no additional bias resistor. The intention behind keeping this node high-Z (in principle, U6 could be omitted altogether) is that the diodes do not draw significant current from the opamps--the current draw would carry lots of harmonic content, which could crosstalk to the main signal path. But a 1 M bias resistor should hardly do much harm.

Samuel
 
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The voltage at the diode summing node is actually not that ill-defined as it looks at first--one of the diodes is always forward-biased, becomes relatively low impedance and delivers the current for the reverse-leakage of the other three. The only problem occurs when the opamp input sources more current than the sum of the reverse-leakage of the diodes. The typical leakage of a 1N4148 is around 10 nA at room temperature and for a few volts reverse-bias. So if U6 becomes a FET input (e.g. a TL072 together with U7), we should be safe even with no additional bias resistor. The intention behind keeping this node high-Z (in principle, U6 could be omitted altogether) is that the diodes do not draw significant current from the opamps--the current draw would carry lots of harmonic content, which could crosstalk to the main signal path. But a 1 M bias resistor should hardly do much harm.

Samuel

If you're really going for SOTA ultra-low distortion, and investing in the extra cost of the 4th order SVO, especially the additional tuning components, you may as well buffer those signals before applying them to the diodes. Then you can implement the diode summing node in an eminently predictable way.

In my own SVO in my THD analyzer, I should have employed such buffering at the agc rectifier take-off point.

http://www.cordellaudio.com/instrumentation/thd_analyzer.pdf

See C4 in Figure 9. But note that the rectifier is built from open-emitter emitter followers, so they provide some buffering in the process.

Cheers,
Bob