FPGA CPLD Altera Xilinx Audio DIY DAC

[elec-tron2]

Hello all diyAudio diyers,

I am currently designing an high end DAC with USB and RCA SPDIF input.

I plan to use a CPLD/FPGA between DAIR and DAC chip but I am woring about the jitter and propagation time ...

Is anybody try this approch ?

I am planning to use this as this enable the use of some custom logic for ie L/R channel separation, upsampling and so on ...

All ideas and comments are welcome

Thank you all

[peufeu]

What is DAIR ?

You can do plenty of stuff with these chips, but they are quite noisy. I presume you will use some reclocking ?

http://audio.peufeu.com

[elec-tron2]

DAIR is chip like CS8412,CS8414...

I do not remember but I think that DAIR is something like Digital Audio Interface Receiver.


Yes and some reclocking too and I would like to try som FIFO too

[peufeu]

Well, FPGAs have RAM and multiply-acculumate units so you can definitly make FIFOs and oversampling with that.

You can even build your system in xilinx ISE (free) and simulate it before you buy parts.

What kind of clock recovery do you plan to use ? VCXO ?

[anbello]

Originally posted by peufeu
Well, FPGAs have RAM and multiply-acculumate units so you can definitly make FIFOs and oversampling with that.

You can even build your system in xilinx ISE (free) and simulate it before you buy parts.

What kind of clock recovery do you plan to use ? VCXO ?

peufeu, from what you say i understand that the use of the internal DDL it's not an option for clock recovery. It's good for data communication but for digital audio too much jitter?

ciao
andrea

[peufeu]

Originally posted by anbello
peufeu, from what you say i understand that the use of the internal DDL it's not an option for clock recovery. It's good for data communication but for digital audio too much jitter?

HELL NO !

First, it's a DDL (delay locked loop). While the clock processing units in Xilinx chips are über powerful (ie. you can specify "multiply clock by 27.5/13" or something) the nature of a FPGA means you have a zillion logic gates running at very high speed, hence the output signal noise and ground noise is horrendous.

It is perfect for clocking the inside of the FPGA and other chips, because at 50 MHz noone will notice 1 ns of jitter as long as it meets timing, but if you feed that to a DAC, it will suck.

IMHO, there are two solutions to get a good clock :

- Master clock in the DAC, end of story
- VCXO controlled by a uC (or a FPGA) if you absolutely need clock slave capability
- analog PLL if you had a brain graft from Guido Tent

[anbello]

hi peufeu, thanks for your replay,
i made confusion between Digital Delay Line (DDL) and Delay Locked Loop (DLL), anyway one object it's used in the other.
An implementation of what you say it's the best option (Master clock in the DAC) could be done (as you and alexandre said in other postings) slaving the transport via an s/pdif link. To have low components count the s/pdif rx (for the data to the DAC) and s/pdif tx (for sending back the clock to the transport) could be implemented in FPGA, on opencores.org there are free s/pdif in and out, i2s in and out, FIFO buffer and many other ip cores.
FPGA could be used also for eventual glue logic, oversampling and FIR filtering.
I know you have done a good job with FPGA, i'am trying to do what i said before but i have so little free time.

ciao
andrea

[peufeu]

In retrospect, I behaved a bit like an industrial designer and bought a FPGA that was adequate for the job, but not much more. I shouldn't have done this. I should have gone straight to the massive overkill of power of the Virtex-4 chip.

It would have cost maybe €100 more, but I wouldn't have lost many many hours working around the idiotic, slow, low-throughput design of this FPGA board.

(The Spartan-3 is a very good chip, but it has so little RAM (48kB) and the DRAM chip generously installed by the boardmaker, and the network chip bus are both horrendously slow).

[elec-tron2]

Well, I am happy to see that this thread is moving

Peufeu, I am happy to have your opinion as I think you are a good designer, in respect this your job available on Internet about amplifier.

So, what do you think about using a FPGA or a CPLD inside a DAC ? Can it have impact (negative or no impact, may be positive impact) on the final sound of the DAC ?

[rfbrw]

A V4 device sounds very nice so long as you don't stop to think about it.