Synchronous Reclocker. Feedback please

[riotubes]

Nothing new here. I'm a novice trying to build a synchronous reclocking circuit for my twin tda1541a unbalanced DAC. Input appreciated. Draft Schematic attached.

Goal:
- Place an 11.2896 XO in external DAC that's fed back to transport
- transport generates bck, lrclk and sdata (assume i2s for the moment)
- In the external dac, these signals get re-synched using 74hc74
- original 11.2896 also drives this reclocking circuit (or "re-synch")
- this is a synchronous connection

I recognize there might be better/preferred ways to accomplish this, but I would appreciate feedback on whether the attachment reflects the stated goal above

Thanks in advance..

[audioengr]

This should work as long as the setup and hold times of the HC74 flip-flops are not violated and the signal voltage levels from the SB are all 5V. If they are 3.3V, then you need to level-shift to 5V. Also, you will need transmission-line terminations at the SB end for the clock input and at the DAC end for the I2S signals, as well as appropriate impedance-matched cables for all of these.

The setup and hold times could be violated even if you change the lengths of the clock and I2S cables. Better to use a buffering scheme so that there are no timing issues and the relationship between the clock coming into the SB and the I2S coming into the DAC are decoupled. My Pace-Car does this BTW.

Steve N.

[riotubes]

This should work as long as the setup and hold times of the HC74 flip-flops are not violated

OH, OK, regarding the cable length and buffering. Your Pace-Car sounds like a dream! I'll research a buffering scheme.

If they are 3.3V, then you need to level-shift to 5V

Do I need to do this for the 1541 Dac's sake? I read that
the SB3 takes a 3.3V logic signal and to get that out of the DAC to that spec because it would be dangerous to feed it a 5V clock. So I was thinking of feeding the XO and reclocker a 3.3V reg low noise supply to heed this warning ???

[audioengr]

Originally posted by riotubes


OH, OK, regarding the cable length and buffering. Your Pace-Car sounds like a dream! I'll research a buffering scheme.



Do I need to do this for the 1541 Dac's sake? I read that
the SB3 takes a 3.3V logic signal and to get that out of the DAC to that spec because it would be dangerous to feed it a 5V clock. So I was thinking of feeding the XO and reclocker a 3.3V reg low noise supply to heed this warning ???

The DAC chip needs 5V levels. If there are 3.3V levels coming from the SB, then you must level-shift them with appropriate buffers. If there is a 3.3V clock currently in the SB, then you must feed it with a 3.3V clock.

Steve N.

[riotubes]

Thanks Steve for your clarification and feedback

As it turns out, the SB3 generates Left Justified Format, not Philips I2S.
The data offset by one bit from the I2S standard (shifted right by 1 bit) and the channels reversed. I've read where in I2S the MSB comes one slot before the LRCK transition, but in left-justified it is immediately after. I read a post by John S in which he said that if its going into an I2S only chip...an extra flip-flop needs to be added to delay the data by one bit period (and swap the interconnects).

How do I incorporate this into my schematic given I need to convert Left Justified Format to i2s. Do I need to add another flop and if so where? thanks!

[riotubes]

On Q in post #5 above....convert left justified to i2s...

[rfbrw]

Originally posted by riotubes

The data offset by one bit from the I2S standard (shifted right by 1 bit) and the channels reversed. I've read where in I2S the MSB comes one slot before the LRCK transition,

That wrong for a start. The I2S spec mandates that the MSB occurs one cycle after the transition of wordclock and the left channel precedes the right channel like any other format. The other difference is wordclock is low for left and high for right. A 74HC74 and an inverter will turn I2S into left justified data.

[riotubes]

OK, so if the transport generates Left Justified signals and my dac accepts I2S, does that mean that in the schematic (attachment in post #1) I add an extra 74HC74 flop after the first flop shown (in the schematic) used for BCK?

FWIW, the schematic as drawn assumes the transport generates i2s, but I suspect you know that. thanks

[rfbrw]

Two flip flops on the data line and invert LRCK.

[riotubes]

OK. Inching closer.

The DAC chip needs 5V levels. If there are 3.3V levels coming from the SB, then you must level-shift them with appropriate buffers. If there is a 3.3V clock currently in the SB, then you must feed it with a 3.3V clock.

How do I do this? Schematic posted in post #1