Help me design a SPDIF reclocker, preferably based on 74hc4046

darkfenriz · 7th December 2006, 10:15 PM

Hi
I want to design a reclocker that is based on typical TTL IC's and a very basic one. I do not nessesary need low jitter, rather a real PLL reclocking based on data bits, not preamble (like in cs8414 or so..)
I am not sure what is the way to amplify SPDIF signal to TTL level as well as wheather I need a frequency divider in PLL.

Please help!
best regards
Adam

gfiandy · 8th December 2006, 12:18 AM

To bring SPDIF to TTL the easiest way is to use 74HCU04 inverters AC coupled at the input with 100n CAP then bias the HCU04s into linear operation by using an input resitor of say 1K and a feedback resistor of 10K. (you may need to optimise these values) Cascade two or three of these to bring the signal up to TTL levels.

The U in HCU04 means they are unbuffered and hence can operate as linear amplifers.

As for using the HC4046 it is well documented in the data sheet first read this. You should be able to set the VCO to operate at 256x Fs (11.2896MHz) and I would use phase comparitor 2. Its the most difficult to get working well but it is much lower noise than the others.

You will need to use an external divider to match the VCO freq to your incomming data frequency. ( I think this is 2.8224MHz approx for SPDIF but I could have remebered it wrong i.e you need to divide by 4)

Not quite sure why you want to do this but this should give you a very jittery but phase locked clock.

Regards,
Andrew

darkfenriz · 8th December 2006, 11:23 AM

Thanks Andrew

That's exactly what I want: low data-induced jitter rejection to check transmission media impact on sound.

regards
Adam

SSassen · 8th December 2006, 12:33 PM

I'm sure you already came across the following, which basically allows you to hit the ground running.

Philips design software 74HCT4046/7046/9046
http://www.standardics.nxp.com/support/pll/pll.zip

Best regards,

Sander Sassen
http://www.hardwareanalysis.com

darkfenriz · 14th December 2006, 10:16 PM

That's how I'd imagine this reclocker to be.
C1 probably will need adjustment.

Please comment.

regards
Adam

rfbrw · 14th December 2006, 11:06 PM

Quote:

Originally posted by darkfenriz

Please comment.

You have actually read the SPDIF specification ?

darkfenriz · 14th December 2006, 11:19 PM

By AES? Not whole, why do you ask?
If something's wrong, than well, If you could help, this ehhmm... would be some kind of ? helpful...

rfbrw · 14th December 2006, 11:48 PM

Quote:

Originally posted by darkfenriz
By AES? Not whole, why do you ask?
If something's wrong, than well, If you could help, this ehhmm... would be some kind of ? helpful...

There are minor design errors and there are Tacoma Narrows sized errors. Your error is so fundamental, the only thing I can say is read and understand the specification

darkfenriz · 15th December 2006, 09:23 AM

Read the specification, datasheets of receivers and Hawksford's publication.
No clue...

rfbrw · 15th December 2006, 10:09 AM

Quote:

Originally posted by darkfenriz
Read the specification, datasheets of receivers and Hawksford's publication.
No clue...

The datastream has the clock embedded in it, is biphase mark encoded and uses code violations to define the channel boundaries.
Which particular edge do you plan to lock to and what do you intend to use as a reference ?

7th December 2006, 10:15 PM	#1
darkfenriz diyAudio Member Join Date: Jun 2004 Location: Warsaw	Help me design a SPDIF reclocker, preferably based on 74hc4046 Hi I want to design a reclocker that is based on typical TTL IC's and a very basic one. I do not nessesary need low jitter, rather a real PLL reclocking based on data bits, not preamble (like in cs8414 or so..) I am not sure what is the way to amplify SPDIF signal to TTL level as well as wheather I need a frequency divider in PLL. Please help! best regards Adam

8th December 2006, 12:33 PM	#4
SSassen diyAudio Member Join Date: Mar 2005 Location: Purmerend	I'm sure you already came across the following, which basically allows you to hit the ground running. Philips design software 74HCT4046/7046/9046 http://www.standardics.nxp.com/support/pll/pll.zip Best regards, Sander Sassen http://www.hardwareanalysis.com __________________ Acception without proper examination equals religion Condemnation without proper examination equals prejudice

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8th December 2006, 12:18 AM	#2
gfiandy Audio Engineer diyAudio Member Join Date: Jul 2003 Location: Cambridge UK	To bring SPDIF to TTL the easiest way is to use 74HCU04 inverters AC coupled at the input with 100n CAP then bias the HCU04s into linear operation by using an input resitor of say 1K and a feedback resistor of 10K. (you may need to optimise these values) Cascade two or three of these to bring the signal up to TTL levels. The U in HCU04 means they are unbuffered and hence can operate as linear amplifers. As for using the HC4046 it is well documented in the data sheet first read this. You should be able to set the VCO to operate at 256x Fs (11.2896MHz) and I would use phase comparitor 2. Its the most difficult to get working well but it is much lower noise than the others. You will need to use an external divider to match the VCO freq to your incomming data frequency. ( I think this is 2.8224MHz approx for SPDIF but I could have remebered it wrong i.e you need to divide by 4) Not quite sure why you want to do this but this should give you a very jittery but phase locked clock. Regards, Andrew

8th December 2006, 11:23 AM	#3
darkfenriz diyAudio Member Join Date: Jun 2004 Location: Warsaw	Thanks Andrew That's exactly what I want: low data-induced jitter rejection to check transmission media impact on sound. regards Adam

14th December 2006, 11:19 PM	#7
darkfenriz diyAudio Member Join Date: Jun 2004 Location: Warsaw	By AES? Not whole, why do you ask? If something's wrong, than well, If you could help, this ehhmm... would be some kind of ? helpful...

15th December 2006, 09:23 AM	#9
darkfenriz diyAudio Member Join Date: Jun 2004 Location: Warsaw	Read the specification, datasheets of receivers and Hawksford's publication. No clue...

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