Hello
I suspect the signal from my cs8416 is filled with jitter on the "recovered master clock" and perhaps the bit clock is not any better. I was thinking that I could insert a pll with slow tuning before the dac. I guess initial tuning should be rather easy when I already have a reference clock and with slow tuning I mean the feedback should be with a relatively large time-constant. With the new clock I can reclock data signal in a way that I don't throw away any samples.
Should I ignore the recovered master clock and derive a 4*(bit clock) from the bit clock to get a 256*fs signal for my dac chip? Does higher system clocks sound better on TI dac chips?
What do you think - is this even possible?
- Christian
I suspect the signal from my cs8416 is filled with jitter on the "recovered master clock" and perhaps the bit clock is not any better. I was thinking that I could insert a pll with slow tuning before the dac. I guess initial tuning should be rather easy when I already have a reference clock and with slow tuning I mean the feedback should be with a relatively large time-constant. With the new clock I can reclock data signal in a way that I don't throw away any samples.
Should I ignore the recovered master clock and derive a 4*(bit clock) from the bit clock to get a 256*fs signal for my dac chip? Does higher system clocks sound better on TI dac chips?
What do you think - is this even possible?
- Christian
It is indeed possible, and IMO the best implementation of this is here:
http://members.chello.nl/~m.heijligers/DAChtml/Build a DAC.htm
OJG
http://members.chello.nl/~m.heijligers/DAChtml/Build a DAC.htm
OJG
I think I'll prefer if the frequency could be tuned to both cd and dvd.
I have tried to simulate different oscillators, but i don't seem to be able to find discrete transistors with enough gain at high frequencies to oscillate in the range 10-50MHz with nice squares. Any suggestions to a VCO I could use?
Will most dac chips enjoy sines as clock signals?
It would be really cool to make the whole PLL circuit with discrete smd's, but I'm afraid it'll act as a transmitter and I might disturb the military frequencies...
No comments about what signal to use for PLL?
Bit-clock or recovered master clock from spdif receiver? I'm thinking that the bit-clock would be the better option.
I have tried to simulate different oscillators, but i don't seem to be able to find discrete transistors with enough gain at high frequencies to oscillate in the range 10-50MHz with nice squares. Any suggestions to a VCO I could use?
Will most dac chips enjoy sines as clock signals?
It would be really cool to make the whole PLL circuit with discrete smd's, but I'm afraid it'll act as a transmitter and I might disturb the military frequencies...
No comments about what signal to use for PLL?
Bit-clock or recovered master clock from spdif receiver? I'm thinking that the bit-clock would be the better option.
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