VHDL and synthesizable models

[rtarbell]

I posted this question on an EDA board (because it's not exactly audio), but I had good luck with this forum, so here goes:

I am new to VHDL, and I understand that not all VHDL code examples are synthesizable into an actual working circuit. In my first project, my goal is to ultimately download the working code into a (cheap) FPGA just to get my hands dirty with the entire process.

Is there a list of commands that I should not use because they are not synthesizable? I don't exacly know how to pick out the commands that will result in a circuit, and the ones that are in VHDL simply to act as models (i.e. unsynthesizable). For instance, in my current code, I use lots of IF THEN statements, and I don't have a clock at all (do I need one, or can I make one using delay statements like "after"?).

Thank you!
-RT

P.S. I'm using quartus II free edition from Altera.

[Funkenstein]

RT,

This thread is a bit old, but I'll answer it in case you're still interested. The list of commands that are not synthesizeable can vary depending on the synthesis software you use. Some of the commands that you generally can't synthesize would be commands like 'wait' and some math commands. For example, the divide '/' may synthesize if it's a simple divider (power of 2) because it will result in a shift operation. Most synthesis engines will not make up a divider if you need something to be divided by '5'.

Regarding your if/then statements. These are no problem but will result in a priority decode if both cases are possible (i.e. the if will be checked before then). If the if/then conditions are mutually exclusive, then the resulting logic will be flattened.

You will need a clock.

-F