help with clock circuit

[pho_boi]

Hi everyone,

I'm trying to add re-clocking to my DAC, which uses the CS8414 receiver chip.

anyway I emailed the shop about it, but they never replied back to me.

I've attached the schematic for it, can someone tell me if this will work with the CS8414?

And is it correct that 44.1KHz clock has to be applied to pin11 and pin12 of the CS8414?

 

[pho_boi]

Ok...

So I did some more reading
- pin12 needs 2.282Mhz
- pin11 needs 44.1Khz

11.2896Mhz is 2^2 multiples of 2.82Mhz

11.2896Mhz is 2^8 multiples of 44.1Khz

So if I was using the 74HC4040 then I would use the output Q2 and Q8, but I'm completely lost when it comes to this 74VHC04!!

 

[regal]

Look at the DDDAC it shows you how to reclock the CS8414

 

[pho_boi]

Look at the DDDAC it shows you how to reclock the CS8414

Hi regal,

I've looked at the dddac design, and I'm familiar with how he implemented the re-clocking. I think it's simple and exactly what I'm looking for.

But the schematic I posted is for a kit I'm interested in, and the price is very good.
So if it could be used to reclock the CS8414, I will just purchase it

 

[pho_boi]

can anyone help?

 

[pho_boi]

bump for me

 

[rfbrw]

but I'm completely lost when it comes to this 74VHC04!!

Have you read the datasheet ?

 

[pho_boi]

Have you read the datasheet ?

Yeah I have, I tried as hard as I could to understand but it doesn't make a whole lot of sense to me.

 

[rfbrw]

Logic does not come much simpler than the inverter. It inverts. Given a pulse train high low high (101), it ouputs low high low (010).

 

[pho_boi]

Logic does not come much simpler than the inverter. It inverts. Given a pulse train high low high (101), it ouputs low high low (010).

What affect does inverting the signal do to the clock?
Will the 11.2896mhz drop down to 44.1Khz? I ask this because I've seen other circuits where this happens, but the inverters they use are different.

sorry for all the newbie questions

 

[rfbrw]

What affect does inverting the signal do to the clock?
Will the 11.2896mhz drop down to 44.1Khz? I ask this because I've seen other circuits where this happens, but the inverters they use are different.

sorry for all the newbie questions

The inverters are buffering the oscillator enabling it to drive multiple loads effectively. Clock division, OTOH, requires something completely different.