Inspired from all the projects going on i will start one myself in this december when my girlfriend allows it 
But i think it is no problem....
I have told her that she can turn everything upside down!, only is she not allowed to touch my sound system!
A picture of the parts to start with :
But i think it is no problem.... I have told her that she can turn everything upside down!, only is she not allowed to touch my sound system!
A picture of the parts to start with :
Attachments
Actually i have dropped my all time favorite Micro's from ATMEL. They are just too hard to get in denmark...
So i am started to learn to use the PIC18 family from microchip.
So for a start project i will use the PIC18F242 together with the PGA2310.
In the same turn i can test the sound stage of the PGA2310.
The PCB for this project will be done at same time as the DAC.
The AD1853 outputs 1mA in bias and 1.5mA p-p on each output.
So right now i am going to figure out if i should make it a discrete or opamp based I/V converter.
Sonny
So i am started to learn to use the PIC18 family from microchip.
So for a start project i will use the PIC18F242 together with the PGA2310.
In the same turn i can test the sound stage of the PGA2310.
The PCB for this project will be done at same time as the DAC.
The AD1853 outputs 1mA in bias and 1.5mA p-p on each output.
So right now i am going to figure out if i should make it a discrete or opamp based I/V converter.
Sonny
Hi, I am also currently drawing up a project with the AD1853, but with a CS8420 on the front end. Are you planning on using 2 1853's (mono mode) , I see 2 in the picture...
Also In a older thread someone mentioned the 1853 automatically reduced the interpolation ratio (8 to 4 to 2) as Fs is increased. Can anyone confirm this? It seems from the data sheet that you can explicitly set the the int. rate via the INT0 and INT1 pins...
Thanks for any insight, and good luck with your design.
-Pete Kunz
Also In a older thread someone mentioned the 1853 automatically reduced the interpolation ratio (8 to 4 to 2) as Fs is increased. Can anyone confirm this? It seems from the data sheet that you can explicitly set the the int. rate via the INT0 and INT1 pins...
Thanks for any insight, and good luck with your design.
-Pete Kunz
answer to the questions :
(ELSO KWAK)
Your discrete FET input inverted cascode design should just work fine!
- Yeah!, i have thought of it. I will do a layout using 2N5912. If i am not happy with it i can always make a layout with a connector matching one on the mainboard. But with another topology!
(takashi)
why you use dir1701 instead of dir1703? any advantage?
- It runs with a 12 or 16MHz crystal until it lock's to the data... And i have a lot of them!!!!
(pjkunz)
Are you planning on using 2 1853's (mono mode)?
- Yes!
Also In a older thread someone mentioned the 1853 automatically reduced the interpolation ratio (8 to 4 to 2) as Fs is increased. Can anyone confirm this?
- No this is from the datasheet. (The interpolation ratio is fixed by software or hardware.)
Master Clock Auto-Divide Feature
The AD1853 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and internally
sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above.
I hope this is some answers!
(ELSO KWAK)
Your discrete FET input inverted cascode design should just work fine!
- Yeah!, i have thought of it. I will do a layout using 2N5912. If i am not happy with it i can always make a layout with a connector matching one on the mainboard. But with another topology!
(takashi)
why you use dir1701 instead of dir1703? any advantage?
- It runs with a 12 or 16MHz crystal until it lock's to the data... And i have a lot of them!!!!
(pjkunz)
Are you planning on using 2 1853's (mono mode)?
- Yes!
Also In a older thread someone mentioned the 1853 automatically reduced the interpolation ratio (8 to 4 to 2) as Fs is increased. Can anyone confirm this?
- No this is from the datasheet. (The interpolation ratio is fixed by software or hardware.)
Master Clock Auto-Divide Feature
The AD1853 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and internally
sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above.
I hope this is some answers!
So just to clarify,
Using an ASRC (CS8420) I can set the interpolation ratio via hardware on the AD1853, independent of the freq? This was my understanding from the datasheet and gives me one more thing to play with. (If not, I don't understand the purpose of setting the INT0 and INT1 Pins). I think this is what you were saying, but wasn't sure which part of my statement your 'no' refered to?
The auto divide will figure out (X) times Fs where (X) is (must be)one of the listed integers, but you are free to set Fs I believe as long as its under 192kHz. The Fs values listed are just the typical values CD,DVD,etc. Am I interpreting this correctly?
-Pete
Using an ASRC (CS8420) I can set the interpolation ratio via hardware on the AD1853, independent of the freq? This was my understanding from the datasheet and gives me one more thing to play with. (If not, I don't understand the purpose of setting the INT0 and INT1 Pins). I think this is what you were saying, but wasn't sure which part of my statement your 'no' refered to?
The auto divide will figure out (X) times Fs where (X) is (must be)one of the listed integers, but you are free to set Fs I believe as long as its under 192kHz. The Fs values listed are just the typical values CD,DVD,etc. Am I interpreting this correctly?
-Pete
okay!, time to a little update.
One of my main concern was that i wanted a really low noise powersupply.
So the Linear regulators has to be made passivly to get noise figures of ~10nV/SQR(Hz) or less.
I also wanted a high PSRR over a wide area. so i got something like 60dB up to 4MHz which i where able to test....
The sim showed something like worstcase 55dB around 10k - 20k.
This within a few days i will upload a Schematic on the Linear regulator for both posetive and negative rails.
Some of the component values will not be given as they have to be optimized for a given load/in and output voltage.
One thing i can say is that it will not of high effiency......
So the design of the DAC will follow the steps shown below.
1) The powersupply.
2) The DIR1701 interface and oscillator ... I will for a start use the build in oscillator.
3) The two AD1853.
4) The I/V converter..... As Elso suggested ... I will use a variant of my JFET preamp.
This starts to build up heavily!!!!
One of my main concern was that i wanted a really low noise powersupply.
So the Linear regulators has to be made passivly to get noise figures of ~10nV/SQR(Hz) or less.
I also wanted a high PSRR over a wide area. so i got something like 60dB up to 4MHz which i where able to test....
The sim showed something like worstcase 55dB around 10k - 20k.
This within a few days i will upload a Schematic on the Linear regulator for both posetive and negative rails.
Some of the component values will not be given as they have to be optimized for a given load/in and output voltage.
One thing i can say is that it will not of high effiency......
So the design of the DAC will follow the steps shown below.
1) The powersupply.
2) The DIR1701 interface and oscillator ... I will for a start use the build in oscillator.
3) The two AD1853.
4) The I/V converter..... As Elso suggested ... I will use a variant of my JFET preamp.
This starts to build up heavily!!!!
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