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Old 16th December 2002, 05:38 PM   #21
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That masterclock and L/R look pretty OK to me.
Dont know about the data signal.

Could you please put L/R and Data on 1 picture ?

No pins floating and etc ?

grtz

Simon
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Old 16th December 2002, 10:08 PM   #22
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From your scope pictures:
(I gleaned the extra precision in these numbers by assuming standard values.)

LRCLK: 44.1KHz (1fs)

MCLK: 11.2896MHz (256fs)

BCLK: 5.6448MHz (128fs) <<<<!!!!!

Width of shortest apparent data bit: 177.2nS (Matches one BCLK cycle).

Calculated width of 24bit data packet: 4.252uS
(It looks like there's only 18 apparent bits).

**********

This Rio device is putting out a 64bit frame size!
32bits is the standard frame size.

The Rio's PCM1716 DAC can handle arbitrary frame size, so this isn't a problem.

Looking at the Crystal CS8405 data sheet (page 6):

Notes: 7. No more than 128 SCLK(your BCLK) per frame...


I think they mean two word frames (i.e. 64bit / channel), so you're right at the limit, but OK.

They have some more restrictions on the phase relationship between signals, that might be the problem.

Could you post DATA, LRCLK and BCLK scanned at the same time?
IF not, could you post three pairs?

Also,
are you probing at the CS8405 end of the connections (rather than where they originate)? It's important to see what the CS8405 is seeing.

Regards,
Brian.
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Old 17th December 2002, 01:24 AM   #23
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I only have access to a dual trace scope. So I won't be able to show three signals together, but I can do pairs. I was getting the signal from the connector that feeds the Crystal board. I assume you are suggesting I instead get them right at the Crystal input pins (12,13,14,21).

I'll try to get the scope out again and post.

With regard to the pins, it looks like from the schematic that 18 and 25 of the CS8405 were left floating.

Thanks again everybody!
Stu
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Old 17th December 2002, 04:45 AM   #24
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If one accepts that the PCM1716 section works, the CS8405A is in hardware mode and configured as a slave and all unused input pins are tied off as needed then signal integrity and, to a lesser extent, the phase relationship between the generated masterclock and the I2S signal is all that is left. Given that you have already tried buffering, have considered tightening up the timing with flip-flops?

ray
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Old 17th December 2002, 09:26 PM   #25
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Quote:
Originally posted by Brian Brown


Could you post DATA, LRCLK and BCLK scanned at the same time?
IF not, could you post three pairs?

Also,
are you probing at the CS8405 end of the connections (rather than where they originate)? It's important to see what the CS8405 is seeing.

Regards,
Brian.
Here are the pictures of each of the signal pairs excluding master clock. They were all taken from the input pins of the CS8405, post buffer.

I have not tried flip flops, but I guess I'll have to look into it.

Thanks again,
Stu

Click the image to open in full size.

Click the image to open in full size.

Click the image to open in full size.
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Old 17th December 2002, 09:52 PM   #26
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Hi Stu,

I'm afraid the sweep rate on this last set of scope plots is way too slow (1mS/div). Also put it back into Sample mode instead of Peak Detect.

To look at the data we'll need sweep rates in the same range that you used the first time. I'd suggest 2uS/div or 1uS/div to begin with.

I'm a little concerned that all of the data lines look about the same: a 1.2KHz square wave. This may just be due to aliasing from the slow sweep rate or from the peak detect mode, but it might also indicate a problem with your interface wiring. If you still see matching signals at the faster sweep rates, go scope the signal pairs back at the Rio board. If they still match, then there's a problem with the way you're probing them with the scope. If they're correct back at the Rio board, then re-examine your wiring.

Also I missed this the first time, but it probably would be better to set the scope's inputs to DC coupling instead of AC coupling. If you could get it to trigger on the falling edge of LRCLK, that would also help.

Let's give it another try.
Brian.
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Old 18th December 2002, 05:49 PM   #27
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Default Second Try!

Brian,

I feel kind of stupid not using your settings the first time, but I am pretty new to using scopes so thanks for bearing with me.

They definitely look different now! SDAT seems a bit off in terms of logic levels.

Thanks again,
Stu

Click the image to open in full size.

Click the image to open in full size.

Click the image to open in full size.
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Old 18th December 2002, 11:33 PM   #28
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Default Aliasing

Hi Stu,

OK, these new pictures are an improvement, but we still need to tweak your scope settings. These are some good concepts to learn while you're still new with scopes.

The time base and scope mode are right now, and we can see the outlines of the packets of data. We're still not seeing all of the individual data bits, though.

In many respects, a digital scope is very similar to PCM digital audio, so what we're seeing might also help some people understand more about digital audio.

What's happening is called 'aliasing'.

Your digital scope takes individual data measurements at regular intervals. It misses anything that might happen with the signal between these measurements. When it displays these measurements, it 'connects the dots' with lines. (It probably has another mode where it just displays the dots without anything in between).

If the signal you are trying to measure changes faster than the scope takes readings (the scope's 'sampling rate'), then the lines connecting the dots in the display don't represent an accurate picture of the signal. That's what's happening here.

A guy named Nyquest came up with a theorem that showed that you need to use a sampling rate that is at least twice the frequency of the signal you are trying to capture. If you exceed Nyquest's limit, then the captured image won't look like the original signal (there weren't enough dots to connect).

(This is why they originally choose 44.1KHz sampling rate for CDs: It's a little over twice the traditionally accepted 20KHz upper range of human hearing.)

The length of the jagged edges of the signals in your display (these are the lines connecting the measurement dots) are about 2uS long. Converting to frequency, this shows that your scope is currently set to a 500KHz sampling rate. I know from your first picture of MCLK that your scope is capable of at least a 100MHz sampling rate, and probably more.

We already know that your MCLK is at 11.2896 MHz, so your scope should be set for a 50MHz sampling rate, or 20nS sample period.

Typically a scope has a certain amount of RAM to store measurements. You then have the option of making a compromise between the sampling rate and the overall length of the sample you are trying to capture. A higher sampling rate gives better resolution of high frequency signals, while a lower sampling rate lets you make a recording for a longer period of time.

Hopefully your scope has enough RAM to capture a full screen of data at 2uS/div at a 50MHz sampling rate. This would require:
50Msamples/second x two channels x 10divisions x 2uS/division = 2000samples. (I don't think this will be an issue).

I don't know the specifics of how to adjust the acquisition settings for your scope, so it might be different than I describe. Hopefully this will at least give you an idea of how to look for it.

Try looking under either the 'horizontal' menu, 'acquire' menu, or 'setup' menu. You should be able to find options like '1000 samples in 20divs'. We want 2000 (or more) samples in 10divs. There might also be a 'fit to screen' option. This would be good to use if it's available.

Hopefully, with a little more tweaking, we'll be able to see what's going on and get back to troubleshooting your problem.

Hang in there,
Brian.
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Old 19th December 2002, 06:33 AM   #29
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Default 8 bclk's in 1 l/r

I hope what i see is completely wrong due to scope settings
but i see 16 bclk in 1 l/r signal.
There should be about 64 !

I hope i can find a propertiming diagram for you ! so you've got comparing material.

grtz


Simon
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Old 19th December 2002, 09:18 AM   #30
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Default i2s signal

hmmmmmmmmmmm,

probably you already have it anyway.

Could you draw a blockdiagram of what you are doing ?


grtz

Simon
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