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Old 13th December 2002, 03:02 PM   #11
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Default Identifying the Format

Several thoughts come to mind here:

First off, as a matter of semantics, I2S (IIS) is a Philips defined protocol with the following features:
The word clock (LRCLK) is low for left channel data.
Data is Left MSB justified with the MSB delayed one count after the LRCLK transition (this makes synchronization with arbitrary frame lengths easier to implement).
The data frame length can be arbitrary, but it is typically 32bits and sometimes 16bits.

Technically, all of the other three wire formats aren't I2S.

You didn't mention if you are able to look at the signals with a 'scope. I think that you're at a point that this will be necessary, since trial and error configuration hasn't worked.

Because you were getting sound from just one channel, this suggests to me either a problem with the frame length or the word clock.

At first I suspected that the RIO device had a 16bit frame and that the CS8405 needed a 32bit frame (many devices have a fixed 32bit frame). This would result in the left channel data being received (almost) properly with the right channel data also being received by the left channel as super low LSBs.

I took a quick glance at the CS8405 data sheet and saw that it appears to support arbitrary word length, so the above probably isn't your problem.

There are other data formats, sometimes called TDM or DSP formats, that are characterized by a short word clock pulse at the begining of the left (or front left) data. This pulse marks the begining of a sequence for all of the data. The right channel data is expected to begin a certain number of counts later, without a transition of the word clock to specifically mark it.

I think there's a good possibility that this may be what you're running into. It could explain all of the symptoms you've described:
The word clock marker pulse deasserts after a couple MSBs of the left channel data have passed. In some modes, the CS8405 would interpret this deassertion as the beginning of a channel. As long as the music data for that channel was below the level being 'clipped' off by the markerpulse, it will come through. The second channel won't have anything to trigger it.

A scope could quickly prove or disprove this theory. If the word clock has a 50% duty cycle, the theory is wrong. If the word clock is a short pulse, then the Rio device is using some sort of TDM mode, which the CS8405 won't support. Offhand I'm not aware of any other transmitter that supports TDM. The best way to deal with this would probably be to use an EPLD to make some format conversion glue logic.

A scope is useful for identifying data formats. Right justified vs. left justified is immediately apparent. I2S can be distinquished from other left justfied formats by the one bit delay.

Hope that helps.
Brian.
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Old 13th December 2002, 04:20 PM   #12
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Thanks Brian for all your insight.

I have not tried a scope yet. I will tonight. Is it possible that the PCM1716 (built in DAC) could work on one of the two aforementioned formats, but not the CS8405? They both seem to support the same formats.

I'll post the results from the scope tonight or tomorrow.

Stu
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Old 13th December 2002, 06:17 PM   #13
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Default I need to pay closer attention.

Quote:
Originally posted by maczrool
Is it possible that the PCM1716 (built in DAC) could work on one of the two aforementioned formats, but not the CS8405?
I missed the point that you had identified the Rio's DAC as a PCM1716. (It's obvious when I re-read the thread).

I looked at the PCM1716 data sheet. It doesn't support any TDM type of formats. So much for that theory...

It still would be useful to try scoping the signals. Let's see what they look like.

Another thought:

Are you sure that the PCM1716 is in software mode? There might be a small chance that the device feeding it is controlling the volume instead. To be sure, look at the MODE pin (p24). If p24 is high, then the PCM1716 is being configured by software. If it's low, then you can look at the other configuration pins. (I know this is a long shot, but I thought I'd ask just in case.)

Could you identify the device generating the signals? It might reveal some more clues.

Brian.
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Old 13th December 2002, 08:33 PM   #14
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Thanks again Brian, you were right about the mode. It's hardware! Pin 24 is low. Format pins 28 and 23 are high, indicating 24 bit I2S format. Odd thing about the volume control, was that although apparently not handled by the DAC, changing the did not lower the volume through the CS8405.

Scope results to come.

The device is a Sonic Blue RioReceiver network MP3 player. It's discontinued, so I can't point you to a website. I believe it uses ~75 mHz ARM processor for decoding.

Stu
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Old 14th December 2002, 03:53 AM   #15
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Does the PLL drive the source of the I2S signals driving the PCM1716 and when you say the masterclock is derived from a 20Mhz source what is used as a reference ?

ray.
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Old 16th December 2002, 03:43 PM   #16
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Here is L/R Clock. Not really sure what to make of them. Have a look.

Thanks,
Stu

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Old 16th December 2002, 03:51 PM   #17
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Here is Master Clock. Not really sure what to make of it. Have a look.

Thanks,
Stu

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Old 16th December 2002, 03:53 PM   #18
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Here is Bit Clock. Not really sure what to make of it. Have a look.

Thanks,
Stu

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Old 16th December 2002, 03:56 PM   #19
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Here is Serial Data. Not really sure what to make of it. Have a look.

Thanks,
Stu

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Old 16th December 2002, 04:00 PM   #20
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Quote:
Originally posted by rfbrw
Does the PLL drive the source of the I2S signals driving the PCM1716 and when you say the masterclock is derived from a 20Mhz source what is used as a reference ?
According to one of the engineers of the device:
"The MCLK is 11.2896MHz. Everything on the board is generated from one xtal [20.0000 MHz] and the Cypress CY2292 chip which has programmable (at production, anyway) dividers/PLLs/etc"
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